CP3SP33SMSSLASHNOPB datasheet(154/407 Pages) TI1

154 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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DISCON

The Disconnect bit enables an interrupt when a device disconnect is detected in Host

mode or a session is ended in Peripheral mode.

0 – No interrupt enabled.

1 – Interrupt enabled.

SESSREQ

The Session Request bit enables an interrupt when a Session Request signal is

detected on the bus. This bit is only valid when the USB controller is an A device.

0 – No interrupt enabled.

1 – Interrupt enabled.

VBUSERROR

The VBUS Error bit enables an interrupt when VBUS drops below the VBUS Valid

threshold during a session. This bit is only valid when the USB controller is an A

device.

0 – No interrupt enabled.

1 – Interrupt enabled.

21.3.9 Frame Register (FRAME)

The Frame register is a 16-bit, read-only register that holds the last received frame number. At reset, this

11M M10

Reserved

FRAMENUMBER

FRAMENUMBER The Frame Number field holds the 11-bit frame number.

21.3.10 Index Register (INDEX)

The Index register is an 8-bit, read/write register that selects the endpoint-specific register bank which is

accessible in the region FF 0810h to FF 081Fh. At reset, this register is cleared to 00h.

4M M3

Reserved

INDEX

The Index field holds the 4-bit endpoint index. Only 0000b, 0001b, 0010b, and 0011b are valid

values.

21.3.11 Endpoint n FIFO Register (EPnFIFO)

The Endpoint n FIFO registers are 32-bit, read/write registers that access the transmit FIFOs when written

and the receive FIFOs when read (n = 0 to 3).

FIFODATA

21.3.12 Device Control Register (DEVCTL)

The DEVCTL register is an 8-bit, read/write register that is used to select whether the USB Controller is

operating in Peripheral mode or in Host mode, and for controlling and monitoring the USB VBus line. After

reset, this register is cleared to 00h.

BDEVICE

FSDEV

LSDEV

VBUS

HOSTMODE

HOSTREQ

SESSION

154

USB Controller

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