CP3SP33SMSSLASHNOPB datasheet(158/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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5M M4

Reserved

LIMIT

The Limit field specifies the Endpoint 0 timeout. A value of 0 or 1 disables the timeout function.

Values from 2 to 16 (decimal) enable the timeout function. Values above 16 are reserved.

21.3.16 Transmit Maximum Packet Size Register (TXMAXP)

The TXMAXP register is a 16-bit, read/write register that specifies the maximum amount of data that can

be transferred through the selected transmit endpoint in a single frame. This value must comply with the

constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous

transactions in full-speed operations. The value should match the wMaxPacketSize field of the Standard

Endpoint Descriptor for the associated endpoint (see Universal Serial Bus Specification Revision 2.0,

Chapter 9). A mismatch could cause unexpected results. The value written to this register must not

exceed the transmit FIFO size. If the value written to this register is less than, or equal to, half the transmit

FIFO size, two packets can be buffered. If this register is changed after packets have been sent from the

endpoint, then the endpoint FIFO should be completely flushed (using the FLUSHFIFO bit in the TXCSR

transmit endpoint (except Endpoint 0). At reset, this register is cleared to 0000h.

11M M10

Reserved

MAXSIZE

The Maximum Packet Size field specifies (in bytes) the maximum payload transmitted in a

single transaction. Valid values for this field are 8, 16, 32, and 64 (decimal).

21.3.17 Transmit Control and Status Register (TXCSR)

The TXCSR register is a 16-bit, read/write register that provides control and status bits for the associated

endpoint (except Endpoint 0). It has different formats in Peripheral and Host modes. After reset, this

Peripheral Mode Format

Reserved

CLRDATATOG

SENTSTALL

SENDSTALL

FLUSHFIFO

UNDERRUN

FIFONOTEMPTY

TXPKTRDY

AUTOSET

ISO

Reserved

FRCDATATOG

Reserved

TXPKTRDY

The Transmit Packet Ready bit is set by software after loading a data packet into the

FIFO. The bit is cleared automatically when the data packet has been transmitted. An

interrupt is asserted (if enabled) when this bit is cleared.

0 – No packet in transmit FIFO.

1 – Data packet in FIFO, ready to transmit.

FIFONOTEMPTY The FIFO Not Empty bit indicates that there is at least one packet in the transmit

FIFO.

0 – Transmit FIFO is empty.

1 – Transmit FIFO is not empty.

UNDERRUN

The Transmit Underrun bit is set when an IN token is received if the TXPKTRDY bit is

clear. Software clears the UNDERRUN bit to detect the next underrun event.

0 – No underrun event detected since the bit was last cleared.

1 – Underrun event detected.

158

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