CP3SP33SMSSLASHNOPB datasheet(112/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Table 18-1. Port Registers (continued)

NAME

ADDRESS

DESCRIPTION

PHDIR

FF CC04h

Port H Direction Register

PHDIN

FF CC08h

Port H Data Input Register

PHDOUT

FF CC0Ch

Port H Data Output Register

PHIEN

FF CC1Ch

Port H Interrupt Enable Register

PHALT

FF CC00h

Port H Alternate Function Register

PHALTS

FF CC18h

Port H Alternate Function Source Register

PHWPU

FF CC10h

Port H Weak Pullup/Pulldown Enable Register

PHPDR

FF CC20h

Port H Weak Pullup/Pulldown Direction Register

In the descriptions of the port registers, the lower-case letter “x” represents the port designation, either E,

F, G, or H. For example, “PxDIR register” means any one of the port direction registers: PEDIR, PFDIR,

PGDIR, or PHDIR.

All of the port registers are 16-bit read/write registers, except for the port data input registers, which are

read-only registers. Each register bit controls the function of the corresponding port pin. For example,

PGDIR.2 (bit 2 of the PGDIR register) controls the direction of port pin PG2.

18.2.1 Port Direction Register (PxDIR)

The PxDIR register selects whether the corresponding port pin is used for input or output. A reset

operation clears the port direction registers, which initializes the pins as inputs.

PxDIR

PxDIR The Port Direction bits select the direction of the corresponding port pin.

0 – Input.

1 – Output.

18.2.2 Port Data Input Register (PxDIN)

The PxDIN register is a read-only register that returns the current state on each port pin. The CPU can

read this register at any time, even when the pin is configured as an output.

PxDIN

PxDIN The Port Data In bits indicate the state on the corresponding port pin.

0 – Pin is low.

1 – Pin is high.

18.2.3 Port Data Output Register (PxDOUT)

The PxDOUT register holds the data to be driven on output port pins. When the pins are configured as

outputs and no alternate function is enabled, writing to this register changes the output value. Reading the

When an interrupt is enabled through the PxIEN register, the PxDOUT register specifies the signal level

which asserts the interrupt.

A warm reset (software reset or watchdog reset) leaves the register contents unchanged. At power-up, the

PxDOUT registers contain undefined data.

112

Input/Output Ports

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