CP3SP33SMSSLASHNOPB datasheet(125/407 Pages) TI1

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Active

Power Save

CPU

Active

Stopped/Slow

System Clock

Main Clock

BT LCC Clock

Active

Stopped

12 MHz

Main Clock

Active

Stopped

1 MHz/12 MHz

BT Clock

Active

Stopped

Sequencer

Enabled

Disabled

HCC

Asserted

Deasserted

HCC

Start-up

CPU Handles

Wake-Up IRQ

from MIWU

CPU

Prepare for

Sleep Mode

DS017

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

4. The Bluetooth sequencer RAM is updated with the code required by the Bluetooth sequencer to

enter/exit Sleep mode.

5. The Bluetooth sequencer RAM and the Bluetooth LLC registers are switched from the HCLK Clock

domain to the local 12 MHz Bluetooth clock domain. At this point, the Bluetooth sequencer RAM and

Bluetooth LLC registers cannot be updated by the CPU, because the CPU no longer has access to the

Bluetooth LLC.

6. Hardware Clock Control (HCC) is enabled, and the CP3SP33 enters a low-power mode (Power Save

or Idle mode). While in Power Save mode, the Slow Clock drives the HCLK Clock. While in Idle mode,

the HCLK Clock is turned off.

7. The Bluetooth sequencer checks if HCC is enabled. If HCC is enabled, the sequencer asserts HCC to

the PMM. On the next rising edge of the low-frequency clock, the 1MHz clock and the 12 MHz clock

are stopped locally within the Bluetooth LLC. At this point, the Bluetooth sequencer is stopped.

8. The M-counter starts counting. After M + 1 Slow Clock cycles, the HCC signal to the PMM is

deasserted.

9. The PMM restarts the 12 MHz Main Clock (and the PLL, if required). The N-counter starts counting.

After N + 1 Slow Clock cycles, the Bluetooth clocks (1 MHz and 12 MHz) are turned on again. The

Bluetooth sequencer starts operating.

10. The Bluetooth sequencer waits for the completion of the sleep mode. When completed, the Bluetooth

sequencer asserts a wake-up signal to the MIWU (see Section 17.0 Section 17).

11. The PMM switches the HCLK Clock to the high-frequency clock and the CP3SP33 enters Active mode

again. HCC is disabled. The Bluetooth sequencer RAM and Bluetooth LLC registers are switched back

from the local 12 MHz Bluetooth clock to the HCLK Clock. At this point, the Bluetooth sequencer RAM

and Bluetooth LLC registers are once again accessible by the CPU. If enabled, an interrupt is issued to

the CPU.

Figure 19-12. Bluetooth Sleep Mode Sequence

19.6 Bluetooth Global Registers

Table 19-2 shows the memory map of the Bluetooth LLC global registers.

Bluetooth Controller

125

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