CP3SP33SMSSLASHNOPB datasheet(129/407 Pages) TI1

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SNOSCW5 – MAY 2013

Figure 20-2. Compensation FIR Filter

By default, the filter applies about 2 dB of compensation at 20 kHz. Five taps is sufficient to allow

passband equalization and ripple cancellation to around ±0.01 dB.

Because the filter must always be phase linear, the coefficients are symmetrical. Coefficients C0, C1, and

C2 are programmable, C3 is equal to C1, and C4 is equal to C0. The maximum power of this filter must

not exceed that of the examples given in Table 20-3.

Table 20-3. Default Filter Coefficients

SAMPLING FREQUENCY

OVER-SAMPLING RATE

(kHz)

125

343

–2291

26984

–2291

343

128

–371

25699

–371

20.4 Reconstruction Filter

The output of the stereo DAC is passed through low-pass reconstruction filters to remove quantization

noise (the “sigma-delta tail”). Because the DAC is optimized for high-quality audio (44.1 kHz or higher

sample rate), the cutoff frequency of the filter is placed at 24 kHz.

At low sample rates (for example, 8 kHz), quantization noise will appear below this cutoff frequency. If the

application requires this noise to be removed, several solutions are possible. For example, low-pass filters

may be added to the DAC outputs. Even simple RC filters will provide substantial noise reduction. Audio

devices intended for voice (such as headsets) often provide an effective filter because of their limited

bandwidth.

In software, digital interpolation may be used to upsample the data for a higher sample rate. This solution

requires no additional hardware, but it consumes more CPU bandwidth and adds delay to the audio path.

20.5 Peripheral Bus Interface

The codec is a slave device on the shared audio peripheral APB bus. As shown in Figure 20-1, the codec

interface has four FIFOs, two read FIFOs for the two ADC channels and two write FIFOs for the stereo

DAC channels. Four independent DMA requests are available corresponding to the four channels. One

interrupt request (IRQ28) is available for triggering by any channel.

20.5.1 FIFOs

The ADC and DAC trigger depths are controlled independently to support differing sampling rates. The full

depth of the FIFOs does not need not be used, and a lesser depth may be used to reduce latency.

Each ADC FIFO remains in the same state when its ADC is disabled and is only cleared during a reset or

flush condition. The ADC FIFOs should be flushed before the ADCs are unmuted to clear any old

samples, or the codec can be placed in reset using the Soft Reset bit (SFTRST bit in the TCDCDEBUG

Telematics Codec

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