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CP3SP33SMS/NOPB Datasheet(PDF) 132 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 132 Page - Texas Instruments |
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132 / 407 page  CP3SP33 SNOSCW5 – MAY 2013 www.ti.com 20.10.1 Codec Basic Configuration Register (TCBCBASIC) The TCDCBASIC register is a 16-bit read/write register that controls the basic operation of the codec. At reset, this register is cleared to 0000h. 7 6 5 4 2 1 0 MUTEL DACOSR DACSTMODE ADC2ON ADC1ON 15 14 13 12 11 10 9 8 DFS AFS FLSDAC FLSADC Reserved SEM MUTER ADC1ON The ADC1 On bit controls whether ADC1 is enabled to run. When written with 1, ADC1 begins its power-up sequence. Check the ADC1UP bit in the TCDCIRQPNDCLR register to determine whether ADC1 has completed its power-up sequence. 0 – ADC1 disabled. 1 – ADC1 enabled. ADC2ON The ADC2 On bit controls whether ADC2 is enabled to run. When written with 1, ADC2 begins its power-up sequence. Check the ADC2UP bit in the TCDCIRQPNDCLR register to determine whether ADC2 has completed its power-up sequence. 0 – ADC2 disabled. 1 – ADC2 enabled. DACSTMODE The DAC Sidetone Mode field controls the basic function of the DAC, sidetone input, and output stage. The sidetone is taken from ADC1. DACSTMODE FIELD LEFT CHANNEL RIGHT CHANNEL 000 Off Off 001 Left Right 010 Left Off 011 Left + Sidetone Off 100 Left + Sidetone Left 101 Left + Sidetone Right 110 Left Right + Sidetone 111 Left + Sidetone Right + Sidetone DOCOSR The DAC Oversampling Rate field selects 32×, 64×, 125×, or 128× oversampling rate for the stereo DAC. Note that the ADCs have a fixed oversampling rate of 125×. 00 – 125× 01 – 128× 10 – 64× 11 – 32× MUTEL The Mute Left-Channel DAC bit controls whether the left-channel DAC will be muted after the next zero-crossing occurs. 0 – Left-channel DAC mute off. 1 – Left-channel DAC mute enabled. MUTER The Mute Right-Channel DAC bit controls whether the right-channel DAC will be muted after the next zero-crossing occurs. 0 – Right-channel DAC mute off. 1 – Right-channel DAC mute enabled. SEN The Status Enable bit controls the clock for the bus interface. When the bus interface is driven with a clock, the power-up and power-down interrupts for the ADCs and DACs may be used. 0 – Bus interface clocks disabled. 1 – Bus interface clocks enabled. 132 Telematics Codec Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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