CP3SP33SMSSLASHNOPB datasheet(134/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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RIGHTFIFO

The Right-Channel DAC FIFO Status field indicates the current status of the FIFO for the

right-channel DAC. After reset, the default mode for this field is to report the number of

empty words available in the FIFO, so it indicates 10h (empty). By setting the DFS bit in

the TCDCBASIC register, this indication is reversed and the field reports the number of

valid words of data. The encoding of the field is the same as that shown for the

LEFTFIFO field.

DACSTATUS

The DAC Status bit indicates whether the DAC output stages are enabled, which may

occur due to remaining charge on the bypass capacitor. Software must check that this bit

has cleared before entering disabling the clock to the codec (or entering a low-power

mode that disables the clock).

0 – DAC off.

1 – DAC on.

20.10.3 Codec ADC Status Register (TCDCADCSTATUS)

The TCDCADCSTATUS register is a 16-bit, read-only register that indicates the current status of the ADC

FIFOs, ADCs, and ADC analog input stage. After ADC operation is enabled in the TCDCADCCLKn and

TCDCBASIC registers, the corresponding ADCnSTATUS bits will become set to indicate that the ADCs

are operational. The ADC FIFOs are unchanged while the ADCs are disabled. While the ADCs are

enabled, the FIFOs can be flushed by using the FLSADC bit in the TCDCBASIC register or by resetting

the codec using the Soft Reset bit (SFTRST bit in the TCDCDEBUG register). After reset, this register is

initialized to 1010h, which indicates the ADC FIFOs contain no valid words and the analog input stage is

powered down.

8 7

5 4

ADC2STATUS

ADC1STATUS

Reserved

ADC2FIFO

Reserved

ADC1FIFO

The ADC1 FIFO Status field indicates the current status of the ADC1 FIFO. After reset,

the default mode for this field is to report the number of empty words in the FIFO, so it

indicates 10h (empty). By setting the AFS bit in the TCDCBASIC register, this indication

is reversed and the field reports the number of valid words of data, as shown below:

ADC FIFO STATUS

AFS BIT

DESCRIPTION

FIELD

00h

Full (16 valid words)

01h to 0Fh

15 to 1 valid words

10h

Empty (no valid data)

1Eh

Underrun error (read while empty)

1Fh

Overrun error (written while full)

00h

Empty (no valid data)

01h to 0Fh

1 to 15 valid words

10h

Full (16 valid words)

1Eh

Underrun error (read while empty)

1Fh

Overrun error (written while full)

ADC2FIFO

The ADC2 FIFO Status field indicates the current status of the ADC2 FIFO. After reset,

the default mode for this field is to report the number of valid words in the FIFO, so it

indicates 10h (empty). By setting the AFS bit in the TCDCBASIC register, this

indication is reversed and the field reports the number of valid words of data. The

encoding of the field is the same as that shown for the ADC1FIFO field.

ADC1STATUS

The ADC1 Status bit indicates whether ADC1 is enabled. If ADC1 is enabled, its clock

must not be disabled.

0 – ADC1 disabled.

1 – ADC1 enabled.

134

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