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CP3SP33SMS/NOPB Datasheet(PDF) 131 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 131 Page - Texas Instruments |
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131 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 If a watchdog reset occurs, the codec’s integral power management will not power down the analog circuitry in a safe manner. When software needs to reset the codec, it should set and then clear the SFTRST bit in the TCDCDEBUG register. 20.8 DC Protection Monitor If the analog outputs are used to drive a loudspeaker differentially, then DC offsets on the outputs can damage the drivers. If the DAC FIFO output has not changed for a programmable number of samples, the DC protection monitor triggers a DAC FIFO flush. If the number of DC protection monitor events exceeds a programmable limit, the monitor can also shut down the stereo DAC. If the DAC is not being used for audio applications and a constant DC output is required, the monitor can be disabled. 20.9 Sidetone Injection Sidetone injection from the ADC1 channel can be enabled individually for each DAC channel. The level of sidetone attenuation is programmable in the SIDETONEATTEN field of the TCDCDSP register from 0 to –36 dB in increments of 3 dB. If the sidetone signal for either channel causes clipping, a warning flag is set (STCLPL or STCLPR in the TCDCDSP register). If the sidetone is used, ADC1 and the stereo DAC must run from the same clock at the same sample and oversampling rate. This can be enabled by setting the CLKTIE bit in the TCDCADC1CLK register and selecting a DAC oversampling rate of 125. 20.10 Telematics Codec Register Set Table 20-4 lists the telematics codec registers. Table 20-4. Telematics Codec Registers NAME ADDRESS DESCRIPTION TCDCBASIC FF 4400h Codec Basic Configuration Register TCDCDACSTATUS FF 4404h Codec DAC Status Register TCDCADCSTATUS FF 4408h Codec ADC Status Register TCDCDSP FF 440Ch Codec DSP Set-Up Register TCDCADCANA1 FF 4410h Codec ADC1 Analog Control Register TCDCADCANA2 FF 4414h Codec ADC2 Analog Control Register TCDCADC1CLK FF 4418h Codec ADC1 Clock Register TCDCADC2CLK FF 441Ch Codec ADC2 Clock Register TCDCDACCLK FF 4420h Codec DAC Clock Register TCDCFIFO FF 4424h Codec FIFO Trigger Control Register TCDCIRQEN FF 4428h Codec Interrupt Enable Register TCDCIRQPNDCLR FF 442Ch Codec Interrupt Pending/Clear Register TCDCCOMPC0 FF 4430h Codec Compensation Filter C0/4 Tap Register TCDCCOMPC1 FF 4434h Codec Compensation Filter C1/3 Tap Register TCDCCOMPC2 FF 4438h Codec Compensation Filter C2 Tap Register TCDCADC1 FF 4448h Codec ADC1 Data Register TCDCADC2 FF 444Ch Codec ADC2 Data Register TCDCLEFT FF 4450h Codec Left-Channel DAC Data Register TCDCRIGHT FF 4454h Codec Right-Channel DAC Data Register TCDCDEBUG FF 443Ch Codec Debug Register TCDCMONITOR FF 4458h Codec Monitor Control and Status Register Copyright © 2013, Texas Instruments Incorporated Telematics Codec 131 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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