CP3SP33SMSSLASHNOPB datasheet(133/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

FLSADC

The Flush ADC FIFO bit can be used to flush the ADC FIFOs. Writing 1 to this bit clears

the FIFOs.

0 – No effect.

1 – Flush the ADC FIFOs.

FLSDAC

The Flush DAC bit can be used to flush the stereo DAC FIFOs. Writing 1 to this bit

clears the FIFOs. This should be used when deliberately pausing the DAC data stream

or any other time when the DAC FIFOs will be underrun deliberately. If the DAC FIFOs

are underrun and this bit is not set, then the DAC is continuously driven with the oldest

data and this will result in a DC component on the DAC outputs.

0 – No effect.

1 – Flush the DAC FIFOs.

AFS

The ADC FIFO Status Mode bit controls the encoding of the ADC1FIFO and ADC2FIFO

fields in the TCDCADCSTATUS register. See the description of the TCDCADCSTATUS

re ister for more information.

DFS

The DAC FIFO Status Mode bit controls the encoding of the LEFTFIFO and

RIGHTFIFO fields in the TCDCDACSTATUS register. See the description of the

TCDCDACSTATUS register for more information.

20.10.2 Codec DAC Status Register (TCDCDACSTATUS)

The TCDCDACSTATUS register is a 16-bit, read-only register that indicates the status of the DAC FIFOs

and the DAC analog output stage. After DAC operation is enabled in the TCDCDACCLK and TCDCBASIC

registers, the DACSTATUS bit will become set to indicate that the DAC is operational. The left and right

DAC FIFOs are clear while the DAC is disabled. While the DAC is enabled, the FIFOs can be flushed by

using the FLSDAC bit in the TCDCBASIC register or by resetting the codec using the Soft Reset bit

(SFTRST bit in the TCDCDEBUG register). The DAC FIFOs should be flushed before the DACs are

unmuted to clear any old samples. After reset, this register is initialized to 1010h, which indicates the DAC

FIFOs contain no valid words and the analog output stage is powered down.

13 12

8 7

5 4

DACSTATUS

Reserved

RIGHTFIFO

Reserved

LEFTFIFO

The Left-Channel DAC FIFO Status field indicates the current status of the FIFO for the

left-channel DAC. After reset, the default mode for this field is to report the number of

empty words available in the FIFO, so it indicates 10h (empty). By setting the DFS bit in

the TCDCBASIC register, this indication is reversed and the field reports the number of

valid words of data, as shown below:

FIFO STATUS FIELD

DFS BIT

DESCRIPTION

00h

Full (16 valid words)

01h to 0Fh

15 to 1 valid words

10h

Empty (no valid data)

1Eh

Underrun error (read while empty)

1Fh

Overrun error (written while full)

00h

Empty (no valid data)

01h to 0Fh

1 to 15 valid words

10h

Full (16 valid words)

1Eh

Underrun error (read while empty)

1Fh

Overrun error (written while full)

Telematics Codec

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