CP3SP33SMSSLASHNOPB datasheet(138/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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20.10.6 Codec ADC Clock Control Register n (TCDCADCnCLK)

The TCDCADCnCLK registers are 16-bit, read/write registers that configure the ADC clock sources.

These registers must only be programmed when the corresponding ADC is disabled. At reset, these

registers are cleared to 0000h.

8 7

Reserved

CLKTIE

ADCCLKSRC

ADCCLKDIV

The ADC Clock Divisor field specifies the ADC clock period in terms of half-cycles of

the input clock. The field is biased by 1, so to get a period of 4 half-cycles, load this

field with 3. A value of zero disables the clock.

ADCCLKSRC

The ADC Clock Source field selects the clock source for the ADC clock divisor.

Independent clock sources can be programmed for each ADC and the DAC, to allow

each section of the codec to run from different clocks. If the sidetone is used, ADC1

and the DAC must run from the same clock source at the same sample and

oversampling rate. Although PLL1 and PLL2 clocks are available as ADC clock

sources, it is recommended to use Auxiliary Clock 4 when a timebase derived from a

PLL is desired.

ADCCLKSRC FIELD

SOURCE

000

PCLK Clock

001

TCIO1 Input

010

PLL2 Clock

011

I2SCLK Input

100

AAI SCK Input

101

Auxiliary Clock 4

110

PLL1 Clock

111

Clock Disabled

CLKTIE

The Clock Tie bit is used to drive the ADC clock from the DAC clock, which causes the

ADCCLKDIV and ADCCLKSRC fields to be ignored. Only the input clock source and

clock divisor are affected by the CLKTIE bit.

0 – ADC clock independent of DAC clock.

1 – ADC clock driven by DAC clock.

20.10.7 Codec DAC Clock Control Register (TCDCDACCLK)

The TCDCDACCLK register is a 16-bit, read/write register that configures the DAC clock source. This

11 10

8 7

Reserved

SEL6_144

DACRNG

DACCLKSRC

DACCLKDIV

The DAC Clock Divisor field specifies the DAC clock period in terms of half-cycles of

the input clock. The field is biased by 1, so to get a period of 4 half-cycles, load this field

with 3. A value of zero disables the clock.

DACCLKSRC

The DAC Clock Source field selects the clock source for the DAC clock divisor.

Independent clock sources can be programmed for each ADC and the DAC, to allow

each section of the codec to run from different clocks. If the sidetone is used, ADC1 and

the DAC must run from the same clock source at the same sample and oversampling

rate. Although PLL1 and PLL2 clocks are available as ADC clock sources, it is

recommended to use Auxiliary Clock 4 when a timebase derived from a PLL is desired.

138

Telematics Codec

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