CP3SP33SMSSLASHNOPB datasheet(139/407 Pages) TI1

139 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

DACCLKSRC FIELD

SOURCE

000

PCLK Clock

001

TCIO1 Input

010

PLL2 Clock

011

I2SCLK Input

100

AAI SCK Input

101

Auxiliary Clock 4

110

PLL1 Clock

111

Clock Disabled

DACRNG

The DACRNG field specifies the expected input clock range of the DAC. This is used by

the power management unit to ensure correct timing during power up and power down.

If the exact clock range is not available, use the next fastest.

TYPICAL SAMPLE RATE

DACRNG FIELD

RANGE (MHz)

(kHz)

SEL6_144

The Select 6 MHz bit is used to select the 6 MHz sync to clock the reconstruction filter,

rather than the 12 MHz clock.

0 – 12 MHz clock.

1 – 6 MHz sync.

20.10.8 Codec FIFO Trigger Control Register (TCDCFIFO)

The TCDCFIFO register is a 16-bit, read/write register that configures the events which assert DMA and

interrupt requests. At reset, this register is cleared to 0000h.

8 7

4 3

DMAR

DMAL

DMAADC2

CMAADC1

DACFIFOTRIG

ADC2FIFOTRIG

ADC1FIFOTRIG

The ADC FIFO Trigger Level field specifies how many empty words are in the ADC1

FIFO when an event is triggered.

ADC2FIFOTRIG

The ADC FIFO Trigger Level field specifies how many empty words are in the ADC2

FIFO when an event is triggered.

DACFIFOTRIG

The DAC FIFO Trigger Level field specifies how many valid words are remaining in

either of the DAC FIFOs when an event is triggered.

DMAADC1

The DMA ADC1 bit enables a DMA request in response to the ADC1 trigger event. If

the ADC1FIFO bit in the TCDCIRQEN register is set, the DMAADC1 bit is ignored.

(Interrupt and DMA requests are mutually exclusive.)

0 – ADC1 DMA request disabled.

1 – ADC1 DMA request enabled.

DMAADC2

The DMA ADC2 bit enables a DMA request in response to the ADC2 trigger event. If

the ADC2FIFO bit in the TCDCIRQEN register is set, the DMAADC2 bit is ignored.

(Interrupt and DMA requests are mutually exclusive.)

0 – ADC2 DMA request disabled.

1 – ADC2 DMA request enabled.

Telematics Codec

139

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