CP3SP33SMSSLASHNOPB datasheet(143/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

GPIO FIELD

I/O

DESCRIPTION

0000

Input

Audio input clock at 256× or 512× oversampling rate

0001

Output

ADC1 Clock

0010

Output

ADC2 Clock

0011

Output

DIGMIC1 Clock

0100

Output

DAC Clock

0101

Output

ADC1 Serial Data Stream

0110

Output

ADC2 Serial Data Stream

0111

Output

Left Channel DAC Serial Data Stream

1000

Output

Right Channel DAC Serial Data Stream

1001

Output

Sidetone Left Overflow

1010

Output

Sidetone Right Overflow

1011

Output

DIGMIC Overflow

1100

Output

1101

Output

>1101

N/A

Reserved

SFTRST

The Soft Reset bit is used to reset the codec independently of a system reset. The codec is

safely reset by setting and then clearing this bit. After the bit is cleared, configuration

registers remain unchanged. The ADC and DAC FIFOs are flushed. Pending interrupts and

DMA requests are cleared. The ADCs and DAC, if enabled, enter their start-up routines to

ensure no noise (click and pop) is heard.

0 – Normal operation.

1 – Soft reset.

20.10.18 Codec Monitor Control/Status Register (TCDCMONITOR)

The TCDCMONITOR register is a 16-bit, read/write register that configures the DC protection monitor. The

monitor ensures that, if the system hangs, harmful DC outputs are not driven to external devices such as

speakers. The monitor is enabled by default. When triggered, it will flush the DAC FIFOs. If the SDE bit is

set and the number of DC protection events exceeds a programmable limit, the protection monitor will also

shut down the stereo DAC. After reset, this register is cleared to 0000h.

Reserved

SDE

SDLIMIT

DCLIMIT

The DC Limit field specifies the number of times a sample can have the same value before

the DC protection monitor is triggered to protect the external device. If the number is less

than 16, a default value of 1023 is used.

The Monitor Disable bit allows software to disable the monitor. By default, the monitor is

enabled until software sets this bit.

0 – Monitor enabled.

1 – Monitor disabled.

SDLIMIT

The Shutdown Limit field is used to specify the number of DC protection events which may

occur before the stereo DAC is shut down. To clear the shutdown condition, software must

respond to the DACDOWN interrupt.

SDE

The Shutdown Enable bit enables stereo DAC shutdown when the monitor is triggered. If a

shutdown event occurs, the stereo DAC remains shut down until this bit is cleared.

0 – DAC shutdown disabled.

1 – DAC shutdown enabled.

Telematics Codec

143

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