CP3SP33SMSSLASHNOPB datasheet(141/407 Pages) TI1

141 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

ADC2UP

The ADC2 Power-Up bit enables an interrupt when ADC2 has powered up.

0 – ADC2 power-up interrupt disabled.

1 – ADC2 power-up interrupt enabled.

DACUP

The DAC Power-Up bit enables an interrupt when the stereo DAC has powered up.

0 – DAC power-up interrupt disabled.

1 – DAC power-up interrupt enabled.

ADC1DOWN

The ADC1 Power-Down bit enables an interrupt when ADC1 has powered down.

0 – ADC1 power-down interrupt disabled.

1 – ADC1 power-down interrupt enabled.

ADC2DOWN

The ADC2 Power-Down bit enables an interrupt when ADC2 has powered down.

0 – ADC2 power-down interrupt disabled.

1 – ADC2 power-down interrupt enabled.

DACDOWN

The DAC Power-Down bit enables an interrupt when the DAC has powered down.

0 – DAC power-down interrupt disabled.

1 – DAC power-down interrupt enabled.

ZXDL

The Zero-Crossing Detector Left Channel bit enables an interrupt when the left-channel

reconstruction filter output crosses zero. This is useful if the gain of an external audio

device is to be changed. Internal gains are controlled automatically on these events.

0 – Zero-crossing interrupt disabled.

1 – Zero-crossing interrupt enabled.

ZXDR

The Zero-Crossing Detector Right Channel bit enables an interrupt when the right-

channel reconstruction filter output crosses zero.

0 – Zero-crossing interrupt disabled.

1 – Zero-crossing interrupt enabled.

MICCLP

The Microphone Clipping bit enables an interrupt when the DIGMIC1 input gain stage

clips.

0 – Microphone clipping interrupt disabled.

1 – Microphone clipping interrupt enabled.

STCLP

The Sidetone Clipping bit enables an interrupt when either sidetone feed to the DACs

clip.

0 – Sidetone clipping interrupt disabled.

1 – Sidetone clipping interrupt enabled.

20.10.10 Codec Interrupt Pending/Clear Register (TCDCIRQPNDCLR)

The TCDCIRQPNDCLR register is a 16-bit, read/write register that indicates the state of pending interrupt

requests. The bits in this register correspond to the interrupt enable bits in the TCDCIRQEN register. A set

bit in the TCDCIRQPNDCLR register indicates that the request is enabled and asserted. The

TCDCIRQPNDCLR register is also used by the interrupt service routine to clear these requests. Writing 1

to a bit in this register clears the request. Writing 0 has no effect. After reset, this register is cleared to

0000h.

ADC1DOWN

DACUP

ADC2UP

ADC1UP

RGTFIFO

LFTFIFO

ADC2FIFO

ADC1FIFO

Reserved

STCLP

MICCLP

ZXDR

ZXDL

DACDOWN

ADC2DOWN

20.10.11 Codec Compensation Filter C0/4 Tap Register (TCDCCOMP0)

The TCDCCOMP0 register is a 16-bit, read/write register that specifies the C0 and C4 coefficients of the

compensation filter, when the CUSTCOMP bit of the TCDCDSP register is set. When the CUSTCOMP bit

is clear, the TCDCCOMP0 register is ignored. After reset, this register is cleared to 0000h

Telematics Codec

141

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 141 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 141 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL