CP3SP33SMSSLASHNOPB datasheet(140/407 Pages) TI1

140 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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DMAL

The DMA Left Channel bit enables a DMA request in response to the left channel

DAC FIFO asserting the DAC trigger event. If the LFTFIFO bit in the TCDCIRQEN

exclusive.)

0 – Left channel DAC DMA request disabled.

1 – Left channel DAC DMA request enabled.

DMAR

The DMA Right Channel bit enables a DMA request in response to the right channel

DAC FIFO asserting the DAC trigger event. If the RGTFIFO bit in the TCDCIRQEN

exclusive.)

0 – Right channel DAC DMA request disabled.

1 – Right channel DAC DMA request enabled.

20.10.9 Codec Interrupt Request Enable Register (TCDCIRQEN)

The TCDCIRQEN register is a 16-bit, read/write register that enables interrupt requests from the codec.

The clock to the TCDCIRQPNDCLR register is enabled when any of the fields in this register are set. After

reset, this register is cleared to 0000h.

ADCDOWN

DACUP

ADC2U

ADC1UP

RGTFIFO

LFTFIFO

ADC2FIFO

ADC1FIFO

Reserved

STCLP

MICCLP

ZXDR

ZXDL

DACDOWN

ADC2DOWN

ADC1FIFO

The ADC1 FIFO bit enables an interrupt when the ADC1 FIFO is filled to the trigger

level specified in the TCDCFIFO register, when the FIFO is full, or when the FIFO is

empty. Setting the ADC1FIFO bit causes the DMAADC1 bit to be ignored. (Interrupt and

DMA requests are mutually exclusive.)

0 – ADC1 FIFO interrupt disabled.

1 – ADC1 FIFO interrupt enabled.

ADC2FIFO

The ADC2 FIFO bit is used to trigger an interrupt when the ADC2 FIFO is filled to the

trigger level specified in the TCDCFIFO register, when the FIFO is full, or when the

FIFO is empty. Setting the ADC2FIFO bit causes the DMAADC2 bit to be ignored.

(Interrupt and DMA requests are mutually exclusive.)

0 – ADC2 FIFO interrupt disabled.

1 – ADC2 FIFO interrupt enabled.

LFTFIFO

The Left DAC FIFO bit enables an interrupt when the left-channel DAC FIFO is emptied

to the trigger level specified in the TCDCFIFO register, when the FIFO is full, or when

the FIFO is empty. Setting the LFTFIFO bit causes the DMAL bit to be ignored.

(Interrupt and DMA requests are mutually exclusive.)

0 – Left-channel FIFO interrupt disabled.

1 – Left-channel FIFO interrupt enabled.

RGTFIFO

The Right DAC FIFO bit enables an interrupt when the right-channel DAC FIFO is

emptied to the trigger level specified in the TCDCFIFO register, when the FIFO is full, or

when the FIFO is empty. Setting the RGTFIFO bit causes the DMAR bit to be ignored.

(Interrupt and DMA requests are mutually exclusive.)

0 – Right-channel FIFO interrupt disabled.

1 – Right-channel FIFO interrupt enabled.

ADC1UP

The ADC1 Power-Up bit enables an interrupt when ADC1 has powered up.

0 – ADC1 power-up interrupt disabled.

1 – ADC1 power-up interrupt enabled.

140

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