ATPL00B datasheet(64/152 Pages) ATMEL

64 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Serial Peripheral Interfaces SPI0 and SPI1

Two Serial Peripheral Interfaces SPI0 and SPI1 are implemented in ATPL00B.

Both SPI0 and SPI1 are full-duplex, synchronous communication bus with two operation modes: master mode and

slave mode. When acting as an SPI master, the microcontroller supports baud rates of up to ¼ of the clock frequency.

The main difference between SPI0 and SPI1 is that while SPI0 is a byte oriented SPI, SPI1 is a byte-buffered SPI. SPI1

byte-buffering will be explained as a special SPI capability type in section 7.3. Ignoring this capability, both SPI0 and

SPI1 are internally identical.

7.1

SPI description

During a byte transfer over SPI, the master and the slave simultaneously transmit (shift out) and receive (shift in) data.

Master is the responsible in SPI system for transfer initialization, proper shifting and sampling of data. Every activity in

the SPI environment is synchronized with the clock signal which is under master

‟s control. A slave select line allows the

master to select the desired slaves to exchange data with; not selected slave devices cannot interfere ongoing bus

activities. In systems with multiple masters, slave select line on the master device can be used to detect multiple master

bus contention.

SPI0 is configured and controlled using three special function registers: SPCTL, SPSTAT and SPDAT. (Similarly, SPI1

is configured and controlled by means of SPCTL1, SPSTAT1 and SPDAT1N registers)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

SPCTL

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

PSC1

PSC0



SSIG: /SS0 slave select ignore, if set to '1' MSTR decides whether the device is a master

or a slave and /SS0 pin can be used as port pin; if set to '0' and MSTR is set to '1' then

the /SS pin decides whether the device is a master or a slave



SPEN: SPI0 enabled '1' or disabled '0', when the SPI0 is disabled the SPI0 pins can be

used as general I/O pins



DORD: SPI0 data order

'1' - the LSB of the data byte is transmitted first

'0' - the MSB of the data byte is transmitted first



MSTR: master '1' / slave '0' mode select. See SSIG field.



CPOL: SPI0 clock polarity

'1'

– SPICLK0 is high when idle, the leading edge of SPICLK0 is the falling edge and

the trailing edge is the rising edge

'0'

– SPICLK0 is low when idle, the leading edge of SPICLK0 is the rising edge and

the trailing edge is the falling edge



CPHA: SPI0 clock phase select

'1' - data is driven on the leading edge of SPICLK0 and is sampled on the trailing

edge

'0' - the first data bit is on the MOSI0/MISO0 line before the first SPICLK0 leading

edge, data is sampled on the leading edge of SPICLK0 and driven on the trailing

edge of SPICLK

ATPL00B Datasheet(PDF) 64 Page - ATMEL Corporation

ATPL00B Datasheet(HTML) 64 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL