ATPL00B datasheet(52/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

5.2

Timer 2

Timer 2 is a 16-bit timer/counter. The count is maintained by two eight-bit timer registers, TH2 and TL2, connected in

cascade. T2MOD and T2CON registers described below control the operation of timer 2.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

T2MOD

TF2SC

EXF2SC

T2PR1

T2PR0

T2OE

DCEN



--: Reserved bit



TF2SC: Timer 2 overflow flag software control. When set to „1‟, TF2 flag must be cleared

by software. When cleared to „0‟, TF2 flag is cleared by hardware when interrupt routine is

vectored



EXF2SC: External Interrupt 2 flag software control. When set to „1‟, EXF2 flag must be

cleared by software. When cleared to „0‟, EXF2 flag is cleared by hardware when interrupt

routine is vectored



T2PR(1:0): Timer 2 preescaler



T2OE: Timer 2 output enable bit. In the timer 2 clock-out mode connects the

programmable clock input to the external pin T2



DCEN: Down count enable bit, configures timer 2 as an up/down counter

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

T2CON

TF2

EXF2

SSI1

SSI0

EXEN2

TR2

C/T2

CP/RL2



TF2: Timer 2 overflow flag, Set by timer 2 overflow. It must be cleared by software. TF2 is

not set when timer 2 is in baud rate generator mode



EXF2: Timer 2 external flag. If EXEN2=‟1‟ capture or reload caused by a negative

transition on T2EX sets EXF2. EXF2 does not cause an interrupt in up/down counter

mode (DCEN=‟1‟)



SSI(1:0): Select T2 as baud rate generator for serial port

“00”: none

“01”: USART0

“10”: USART1

“11”: USART2



EXEN2: Timer 2 external enable bit. Setting EXEN2 causes a capture or reload to occur

as a result of a negative transition on T2EX unless timer 2 is being used as baud rate

generator. Clearing EXEN2 causes timer 2 to ignore events at T2EX



TR2: Timer 2 run control bit. Setting this bit starts the timer



C/T2: Timer 2 counter/timer select. When set it selects counter operation then timer 2

counts negative transitions on system clock



CP/RL2: When set to „1‟, captures occur on negative transitions at T2EX if EXEN=‟1‟;

When cleared to „0‟, auto reload occurs on timer 2 overflow or negative transitions at

T2EX if EXEN2=`1`. If RCLK=‟1‟ or TCLK=‟1‟ the CP/RL2 bit is ignored

Timer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate generator mode, and

programmable clock-out mode. Select the operating mode with T2MOD and T2CON register bits as shown in Table 5-1.

Auto-reload is the default mode. Setting T2CON(5:4) selects the baud rate generator mode.

ATPL00B Datasheet(PDF) 52 Page - ATMEL Corporation

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