ATPL00B datasheet(66/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Table 7-1.

SPI0 port map

ADD8051C3A Port

Alternate Function

P5.0

/SS0

P5.1

SPICLK0

P5.2

MOSI0

P5.3

MISO0

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave

on the MOSI (Master Out Slave In) pin and flows from slave to master on the MISO (Master In Slave Out) pin. The

SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN

(SPCTL.6) = 0 (reset value), these pins can be used as general purpose I/O pins.

SS is an optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI

device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected or not. The SS is

ignored if any of the following conditions are true:

The SPI0 system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value)

SPI0 is enabled but SS pin is not needed in such system, i.e. SSIG(SPCTL.7) = 1; in this case SS pin can be

used as general purpose pin on P5.

7.1.2

SPI clock phase, polarity and operation

There are four combinations (CPHA, CPOL) for sampling and shifting activities on data and clock lines in the SPI.

Master can switch between any of them at any time thus having ability to communicate with slaves supporting data

transfer using different modes.

In order to have successful data transfer between SPI devices, proper selection of the SPI clock phase and polarity is

crucial. It is important to note that some of these configurations offer less capabilities than others. Clock Phase Bit

CPHA allows user to specify the edges for sampling and shifting data. Clock Polarity bit CPOL allows user to set the

clock polarity Figure 7-2 and Figure 7-3 show transfers with different values of CPHA and CPOL.

The SPI clock preescaler selection uses the PSC1-PSC0 bits in the SPCTL register and PSC2 in SPSTAT register.

Master selects one of the available baud rates for the SPI communication. SPI Clock Preescaler bits do not have affect

on the part acting as a slave, since it uses SPI clock supplied by the master.

When microcontroller operates as a slave with CPHA=‟0‟, some restrictions are present.

SSIG must be „0‟ and the SS pin must be negated and reasserted between each successive byte transfer.

If the SPDAT register is written while SS is active (low), a write collision error results.

Microcontroller‟s behavior is undefined if CPHA is „0‟ and SSIG is „1‟.

On the other hand, slave having CPHA=‟1‟ may set SSIG to „1‟. If SSIG = 1, the SS pin may remain active low between

successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed

master

and a single slave driving the MISO data line. Microcontroller configured as a master with CPHA=‟0‟ does not

need to negate and reassert slave‟s SS line in order to send and receive byte(s) of data.

In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN = 1) and microcontroller is configured

as SPI master, writing to the SPI data register by the master will start the SPI clock generator and data transfer. The

data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.

ATPL00B Datasheet(PDF) 66 Page - ATMEL Corporation

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