ATPL00B datasheet(42/152 Pages) ATMEL

42 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

PT2

PSPI

PS0

PT1

PX1

PT0

PX0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

IPH

PT2H

PSPIH

PS0H

PT1H

PX1H

PT0H

PX0H



-- : Reserved bit



[IPH(6),IP(6)] : PT2 defines timer 2 interrupt priority level



[IPH(5),IP(5)] : PSPI defines serial peripheral interface SPI0 interrupt priority level



[IPH(4),IP(4)] : PS0 defines serial port 0 interrupt priority level



[IPH(3),IP(3)] : PT1 defines timer 1 interrupt priority level



[IPH(2),IP(2)] : PX1 defines external interrupt 1 priority level



[IPH(1),IP(1)] : PT0 defines timer 0 interrupt priority level



[IPH(0),IP(0)] : PX0 defines external interrupt 0 priority level

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

IP2HL

PSPI1_1

PSPI1_0

PS2_1

PS2_0

PS1_1

PS1_0



IP2HL(7:6) : PSPI1 defines serial peripheral port 1 SPI1 priority level



IP2HL(5:4) : PS2 defines serial port 2 priority level



-- : Reserved bit



IP2HL(1:0) : PS1 defines serial port 1 priority level

A low-priority interrupt can only be interrupted by a higher priority interrupt (but neither by another low-priority nor an

equal-priority interrupt).

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is served. If

interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which

request is served. Thus within each priority level there is a second priority structure determined by the polling sequence

as follows:

10.

IE0

TF0

IE1

TF1

RI+TI

SPI0

TF2+EXF2

RI1+TI1

RI2+TI2

SPI1

(highest priority)

(lowest priority)

ATPL00B Datasheet(PDF) 42 Page - ATMEL Corporation

ATPL00B Datasheet(HTML) 42 Page - ATMEL Corporation

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