ATPL00B datasheet(44/152 Pages) ATMEL

44 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

4.6.3

Interrupt Handling

External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and

IT1 in Register TCON. When external interrupts are transition-activated the INTx pin must show a high level in one

cycle and a low level in the next cycle to generate the interrupt, so that an input high or low should hold for at least 1

machine cycle to ensure sampling. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. The

flags are cleared by hardware when the service routine is vectored only if the interrupts are transition-activated. When

the interrupts are level-activated the interrupt flags are controlled by the external source, so that the external source has

to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.

The response time is always more than 3 machine cycles and less than 7 machine cycles depending on program

execution and interrupt status (see Figure 4-12).

Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover. The flags are cleared by the

on-chip hardware when the service routines are vectored.

Timer 2 interrupts (TF2 and EXF2) are user configurable, and depending on configuration flags will be cleared by

hardware or by user software.

Serial Ports Interrupts are generated by the logical OR of RI and TI. They must be cleared by software.

SPI interrupts must be cleared by software.

Figure 4-12. Interrupt Handling

All of the bits that generate interrupts can be set or cleared by software. That is, interrupts can be generated or pending

interrupts can be canceled by software. Each of these interrupt sources can be individually enabled or disabled by

setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all

interrupts at once.

The interrupt flags are sampled at every machine cycle. The samples are polled during the following machine cycle. If

one of the flags was in a set condition at the preceding cycle, the polling cycle will find it and the interrupt system will

generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any

of the following conditions:

Condition 1. An interrupt of equal or higher priority level is already in progress.

Condition 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.

Condition 3. The instruction in progress is RETI or any write to the IE or IP registers.

S2 S3

S1 …. S3

S1 …. S3 S1 …. S3

interrupt

latching

interrupt

polling

hardware LCALL

to interrupt code

interrupt code

2nd interrupt polling

executed when previous polling is blocked

S2 S3

S1 …. S3

S1 …. S3 S1 …. S3

interrupt

latching

interrupt

polling

hardware LCALL

to interrupt code

interrupt code

2nd interrupt polling

executed when previous polling is blocked

ATPL00B Datasheet(PDF) 44 Page - ATMEL Corporation

ATPL00B Datasheet(HTML) 44 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL