ATPL00B datasheet(69/152 Pages) ATMEL

69 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Figure 7-5.

SPI single master with multiple independent slaves configuration

In Figure 7-5

, slave‟s SSIG = 0, and SS is used to select the slave. The SPI0 master can use any port pin (including

P5.0/SS with SSIG = 1) to drive the SS pin.

Multimaster configuration is the case where two devices are connected to each other and either device can be a master

or a slave. When no SPI0 operation is occurring, both can be configured as masters (MSTR = 1) with SSIG = 0 and

P5.0 (SS) being in quasi-bidirectional mode. Before device initiates a transfer, it must set SSIG = 1 in order to avoid its

own mode change since it will drive P5.0 low, forcing a mode change in the other device to slave.

Table 7-2 shows configuration for the master/slave modes in various cases.

Table 7-2.

SPI modes

SPEN

SSIG

MSTR

operation

MISO

MOSI

SPICLK

comment

P5.0

(1)

disabled

P5.3

(1)

P5.2

(1)

P5.1

(1)

SPI0 disabled, P5(3:0)

are used as port pins

slave

out

selected as slave

slave

not selected, MISO is H

to avoid bus contention

1(=>0)

(2)

slave

out

the uC is configured as

a master, then it is

selected by SS to be a

slave, MSTR bit is

cleared and the uC

becomes a slave

master

out

P5.0

(1)

slave

out

slave not needing SS

P5.0

(1)

master

master not needing SS

Notes:

function as port or as alternate output function

the MSTR bit changes to „0‟ automatically when SS becomes low in input mode and SSIG is 0

SPI Clock

Generator

SPI MASTER

SPI SLAVE A

SPI SLAVE B

8bit Shift Register

MISO

MOSI

SPICLK

PORT A

/SS

MISO

MOSI

SPICLK

/SS

8bit Shift Register

ATPL00B Datasheet(PDF) 69 Page - ATMEL Corporation

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