ATPL00B datasheet(49/152 Pages) ATMEL

49 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Timers

The ADD8051C3A has a full set of timers, listed below:

Two 16-bit configurable Timers/Counters: Timer 0 and Timer 1 that can be configured as timers or event

counters.

Three 8-bit auto reload counters Timers 11, 12 and 14, used as baud rate generators for uarts 0, 1 and 2

respectively (see Standard Serial Interfaces section).

One 8-bit, with 18-bit preescaler, watchdog timer: Timer 3 (see Watchdog (timer 3) section).

One 16-bit Timer/Counter Timer 2 with capture reload hardware (see 5.2)

5.1

Timer 0 and Timer 1

Timers 0 and 1 have 2-bit preescalers. These preescalers can be programmed to slow down count rate. The reset value

set the preescaler values to the slowest count rate and the real count rate of the timers is the same than the timers in an

“8051 legacy” microcontroller (12 clock cycles per machine cycle).

TPR, TMOD and TCON registers described below are involved in timer 0 and timer 1 management.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

TPR

T1P1

T1P0

T01P1

T01P0

T0P1

T0P0



--:

Reserved bit



T1P(1:0): Rollover value for T1 preescaler when T1 is in modes 0, 1, 2 and 3



T01P(1:0): Rollover value for TH0 preescaler when T0 is in mode 3



T0P(1:0): Rollover value for T0 preescaler when T0 is in modes 0, 1, and 2, and for TL0

preescaler when T0 is in mode 3

When T0 or T1 are in the timer function, the registers are incremented every 1, 2, 3 or 4 machine cycles. Since a

machine cycle consists of 3 oscillator periods, the count rate is 1/3, 1/6, 1/9 or 1/12 of the oscillator frequency.

In the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input

pin, T0(P3.4) or T1(P3.5). When in counter function, the external input is sampled once every machine cycle. When the

samples show a high in one cycle and a low in the next cycle (1-to-0 transition), the count is incremented. The register

value is updated during the cycle following the one in which the transition was detected, the maximum count rate is 1/2

of the machine cycle frequency.

Either the timer or counter function is selected by control bit C/T in the Special Function Register TMOD where T0 and

T1 have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD.

TIMER 1

TIMER 0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

TMOD

GATE

C/T

GATE

C/T



GATE:

„1‟: Enables gate control. Device count is enabled only when both „INTi‟ pin and

“TCON.TRi” are high.

„0‟: Disables gate control. Device count is enabled when “TCON.TRi” is high.



C/T:

„1‟: Counter operation mode. Input from Ti input pin

ATPL00B Datasheet(PDF) 49 Page - ATMEL Corporation

ATPL00B Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL