ATPL00B datasheet(71/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

SPSTAT1

SPIF

WCOL

PSC2



--: Reserved bit



SPIF: SPI1 transfer completion flag. When ESPI1 (IE2.3) bit and EA (IE.7) bit are '1' and

a SPI1 transfer finishes then the SPIF bit is set by hardware and an interrupt is

generated. SPIF will also be set when SPI1 is in master mode with SSIG(SPCTL1.7)='0'

and /SS(slave select) pin is driven low



WCOL: SPI1 write collision flag. The WCOL bit is set by hardware when SPDAT is written

during a data transfer. WCOL flag is cleared in software by writing '0' to this bit.



PSC2: SPI1 master clock rate select msb



N(2:0): Number of additional bytes to transfer in SPI1

The data bytes to be transferred must be written in order. Transfer will start when SPDAT1N is written if

N=SPSTAT(2:0).

A write collision will occur if any SPDAT1N (with N<=SPSTAT(2:0)) is written before the 1+N bytes transfer is finished.

Table 7-3.

SPI1 port map

ADD8051C3A Port

Alternate Function

P4.2

/SS1

P4.3

SPICLK1

P4.4

MOSI1

P4.5

MISO1

ATPL00B Datasheet(PDF) 71 Page - ATMEL Corporation

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