ATPL00B datasheet(34/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Table 4-6.

Data Transfer Instructions that access External Data Memory Space

ADDRESS

MNEMONIC

OPERATION

EXECUTION TIME (mc)

WIDTH

8 bits

MOVX A,@Ri

Read external RAM @Ri

8 bits

MOVX @Ri,A

Write external RAM @ Ri

16 bits

MOVX A,@DPTR

Read external RAM @ DPTR

16 bits

MOVX @DPTR,A

Write external RAM @ DPTR

Code Constants

Table 4-7 shows the two instructions that are available for reading code constants in Program Memory. Since these

instructions access only Program Memory, the code constants can only be read, not updated.

The mnemonic is MOVC for “move constant”. The first MOVC instruction in Table 4-7 can accommodate a table of up to

256 entries numbered 0 through 255. The number of the desired entry is loaded into the Accumulator, and the Data

Pointer is set up to point to the beginning of the table. Then, MOVC A,@A+DPTR copies the desired table entry into the

Accumulator.

The other MOVC instruction works the same way, excepting that the Program Counter (PC) is used as the base

address: MOVC A,@A+PC

Table 4-7.

Code Constants Read Instructions

MNEMONIC

OPERATION

EXECUTION TIME (mc)

MOVC A,@A+DPTR

Read program memory at (A + DPTR)

MOVC A,@A+PC

Read program memory at (A + PC)

4.4.6

Boolean Instructions

80C51 devices contain a complete Boolean (single-bit) processor. The internal RAM contains 128 addressable bits, and

the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one

can be treated as a separate single-bit port. The instructions that access these bits are not just conditional branches,

but a complete menu of move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not

easily obtained in other architectures with any amount of byte-oriented software. The instruction set for the Boolean

processor is shown in Table 4-8. All bit accesses are by direct addressing.

Bit addresses 00H through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR space.

The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer to

the Carry bit as C assemble as Carry-specific instructions (CLR C, etc.). The Carry bit also has a direct address, since it

resides in the PSW register, which is bit-addressable.

Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR) operation.

There is a series of bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the

addressed bit is not set (JNC, JNB). JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a

flag can be tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity bit, or the

general purpose flags, for example, is also available to the bit-test instructions.

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