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ATPL00B Datasheet(PDF) 38 Page - ATMEL Corporation |
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ATPL00B Datasheet(HTML) 38 Page - ATMEL Corporation |
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38 / 152 page  Atmel ATPL00B [datasheet] 43028A-ATPL - 9/12 38 Figure 4-10. Bus timing in 8051C3A 4.5.1 Reset ATPL00B can be reset in different ways, listed and explained below External reset. The external reset input signal is RSTA which is an asynchronous reset. Every time RSTA signal is asserted, the boot loader is triggered (thus, microcontroller is halted, target program from the serial flash is uploaded to the internal SRAM, and then microcontroller is released to begin program execution). In power-on, D_INIT must be set before RSTA in order to ensure proper system start up. Software reset AUX1(5) = AUX1.SRST. This field in AUX1 SFR forces the microcontroller to start program execution from PC=0, and all the SFRs are initialized to their reset default values. This reset doesn‟t affect the boot loader reload. Software reset CONF(2) = CONF.RLD. This field is directly connected to boot loader reload input. Every time the microcontroller sets this field, the boot loader is triggered. S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN (a) Program execution without MOVX RD (b) Program execution with a read MOVX WR ADD PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7 PC+8 PC+9 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+5 OPC+6 OPC+7 OPC+8 OPC+9 OPC+.. S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN RD WR ADD PC PC+1 XX PC+2 PC+3 PC+4 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+.. READ ADD READ DATA ZZ ZZ ZZ (c) Program execution with a write MOVX S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN RD WR ADD PC PC+1 XX PC+2 PC+3 PC+4 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+.. WRITE ADD WRITE DATA ZZ ZZ CPU state wri dec exe wri dec exe wri dec exe wri dec S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN (a) Program execution MOVX RD (b) Program execution a read MOVX WR ADD PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7 PC+8 PC+9 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+5 OPC+6 OPC+7 OPC+8 OPC+9 OPC+.. S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN RD WR ADD PC PC+1 XX PC+2 PC+3 PC+4 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+.. READ ADD READ DATA ZZ ZZ ZZ (c) Program execution a write MOVX S3 S2 S2 S1 S1 S3 S3 S2 S1 CLOCK PSEN RD WR ADD PC PC+1 XX PC+2 PC+3 PC+4 PC+.. DATA OPC+1 OPC OPC+2 OPC+3 OPC+4 OPC+.. WRITE ADD WRITE DATA ZZ ZZ CPU state wri dec exe wri dec exe wri dec exe wri dec |
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