ATPL00B datasheet(45/152 Pages) ATMEL

45 / 152 page

Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures

that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the

instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any

interrupt is vectored to.

The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at the

previous machine cycle. The polling cycle/LCALL sequence is illustrated in Figure 4-12.

The hardware-generated LCALL executes a program jump to fixed program entries as shown below:

Table 4-12. Fixed Program entries

Source

Vector

Address

IE0

0003H

TF0

000BH

IE1

0013H

TF1

001BH

RI0+TI0

0023H

SPI0

002BH

TF2+EXF2

0033H

RI1+TI1

003BH

RI2+TI2

004BH

SPI1

0053H

Execution proceeds from that location until the RETI instruction is encountered then the interrupted program continues

from where it left off.

4.7

I/O Ports

The ports P1, P3, P4 and P5 in the ADD8051C3A are bidirectional. Each port consists of a register (Special Function

Registers P1, P3, P4, P5), an output driver, and an input buffer.

Pins in ports 3, 4 and 5 are multifunctional. They are port pins and also serve as input or output for the microcontroller

peripherals:

ATPL00B Datasheet(PDF) 45 Page - ATMEL Corporation