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ATPL00B Datasheet(PDF) 33 Page - ATMEL Corporation

Part # ATPL00B
Description  FSK Power Line Communications SoC
PDF  152 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATPL00B Datasheet(HTML) 33 Page - ATMEL Corporation

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Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
33
4.4.5
Data Transfer Instructions
Internal RAM
Table 4-5 shows the menu of instructions that are available for moving data around within the internal memory spaces,
and the addressing modes that can be used with each one. All of these instructions are executed in 1 mc.
Table 4-5.
Data Transfer Instructions that Access Internal Data Memory Space
MNEMONIC
OPERATION
ADDRESSING MODES
EXE
CUTI
ON
DIR
IND
REG
IMM
TIME
(mc)
MOV A,<src>
A = <src>
X
X
X
X
1
MOV <dest>,A
<dest> = A
X
X
X
1
MOV <dest>,<src>
<dest> = <src>
X
X
X
X
1
MOV DPTR,#data16
DPTR = 16-bit immediate constant
X
1
PUSH <src>
INC SP:MOV“@SP”,<src>
X
1
POP <dest>
MOV <dest>,“@SP”:DEC SP
X
1
XCH A,<byte>
ACC and <byte> exchange data
X
X
X
1
XCHD A,@Ri
ACC and @Ri exchange low nibbles
X
1
The MOV <dest>, <src> instruction allows data to be transferred between any two internal RAM or SFR locations
without going through the Accumulator. Remember, the upper 128 bytes of IDATA can be accessed only by indirect
addressing, and SFR space only by direct addressing.
Note that in any 80C51 device, the stack resides in on-chip RAM, and grows upwards. The PUSH instruction first
increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP use only direct addressing to
identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register.
This means the stack can go into the Upper 128 bytes of RAM, if they are implemented, but not into SFR space.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data Pointer (DPTR) for look-up
tables in Program Memory, or for 16-bit external Data Memory accesses.
The XCH A, <byte> instruction causes the Accumulator and addressed byte to exchange data. The XCHD A, @Ri
instruction is similar, but only the low nibbles are involved in the exchange.
External RAM (from microcontroller point of view)
Table 4-6 shows a list of the Data Transfer instructions that access external Data Memory. Only indirect addressing can
be used. The choice is whether to use a one-byte address, @Ri, where Ri can be either R0 or R1 of the selected
register bank, or a two-byte address, @DPTR. All of these instructions execute in 2 mc.
Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of the data.
The read and write strobes to external RAM are activated only during the execution of a MOVX instruction.



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