ATPL00B datasheet(76/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

8.3

System startup

When the system is configured in execution mode (/PROG pin is set) and after a power up or reload process, the boot

loader checks the system configuration and performs the required operations to ensure the correct execution of the

firmware.

Boot loader transfers a volatile copy of the firmware from the flash memory to the SRAM memory starting at address

000000 (Hex). The internal SRAM size is 128Kbytes and the maximum SPI flash size supported is 16Mbits. The part of

the SRAM that is not used to store the firmware is used by the system to store the volatile data in the execution

process.

The volatile data is stored in the SRAM memory from top to bottom. This arrangement is done automatically by the

system, that is, when the microcontroller wants to save data at address A the system automatically converts the target

address to (top address

– A). Using this storage method, the amount of volatile data that can be stored in the RAM is

determined by the firmware size.

The transfer process can last about 400ms depending on flash device and code size. The first time this process will be

longer if auto encryption is activated. Auto encryption must be done once, and care must be taken about respecting

encryption times.

When the transfer process is finished, the microcontroller begins to execute the program and the system is ready to

use. The startup cycle is performed each time the system is powered up or when the microcontroller via software or

watchdog forces a firmware reload process writing in a specific register.

Both the location of the firmware at the SPI flash and the transfer size are configurable. The lower six bytes of the SPI

flash are used to store the initial and final position of the firmware (from address 0x000000 to 0x000005).

This feature allows working with a SPI flash device that has multiple firmware versions stored in different addresses.

The version to be used can be selected by means of its initial and final addresses.

The transfer size is equal to the firmware size.

Bank-switching is supported, so firmware code bigger than 64KB can be managed. Extreme caution must be taken

when using bank-switching in order to respect code and variables spaces and avoid overlapping.

Figure 8-4.

Flash & SRAM memories diagram

02FFFF

020000

FIRMWARE 1

FIRMWARE 2

000000

010000

01FFFF

1FFFFF

SPI FLASH MEMORY

RAM MEMORY

INITIAL ADDRESS = 020000

FINAL ADDRESS = 02FFFF

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