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H5GQ2H24AFR-R0C Datasheet(PDF) 171 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C Datasheet(HTML) 171 Page - Hynix Semiconductor |
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171 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 171 H5GQ2H24AFR Figure 89. Scan Shift Timing tSES tSCS tSCS tSAC Scan Out bit 1 Scan Out bit 2 Scan Out bit 3 Scan Out bit 4 tSOH SCK SEN SOUT SSH SOE# VDD VDDQ VREF RESET# (SSH in Scan Mode) SEN tSES SCK SOE# tSAC SOUT Pins under Test VALID tSDS tSDH Scan Out bit 1 tSCK 200us Power‐up VDD stable Don’t Care tSCS tSCS tSCS Boundary Scan Mode RESET at power‐up Figure 90. Scan Initialization Sequence |
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