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STC12LE5616AD Datasheet(PDF) 101 Page - STCmicro Technology Co,.Ltd |
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STC12LE5616AD Datasheet(HTML) 101 Page - STCmicro Technology Co,.Ltd |
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101 / 377 page  Operation: DJNZ (PC) ← (PC) + 2 ← (PC) + 2 (PC) + 2 (direct) ← (direct) – 1 ← (direct) – 1 (direct) – 1 IF (direct) > 0 or (direct) < 0 THEN (PC) ← (PC) + rel ← (PC) + rel (PC) + rel INC <byte> Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FFH will overflow to 00H.No flags are affected. Three addressing modes are allowed: register, direct, or register- indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The instruction sequence, INC @R0 INC R0 INC @R0 will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 41H. INC A Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 0 0 Operation: INC (A) ← (A)+1 ← (A)+1 INC Rn Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 1 r r r Operation: INC (Rn) ← (Rn)+1 ← (Rn)+1 INC direct Bytes: 2 Cycles: 1 Encoding: 0 0 0 0 0 1 0 1 direct address Operation: INC (direct)←(direct) ←(direct) (direct) 101 |
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