STC12LE5616AD datasheet(125/377 Pages) STC

125 / 377 page

STC12C5620AD series support 9 interrupt sources with four priority levels. The 9 interrupt sources are external

interrupt 0(INT0), Timer 0 interrrupt, external interrupt 1(INT1), Timer 1 interrrupt, serial port 1(UART)

interrupt, ADC and SPI interrupt, low voltage detector (LVD) and PCA interrupt. Each interrupt source has one

or more associated interrupt-request flag(s) in SFRs. Associating with each interrupt vector, the interrupt sources

can be individually enabled or disabled by setting or clearing a bit (interrupt enalbe control bit) in the SFRs IE,

CCON.

However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 be-

fore the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt

sources regardless of the individual interrupt-enable settings.

If interrupts are enabled for the source, an interrupt request is generated when the interrupt-request

flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL

to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must

end with an RETI instruction, which returns program execution to the next instruction that would have

been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-

pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-

pending flag is set to logic 1 regardless of the interrupt’s enable/disable state.)

Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and

other in IP register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two

interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.

If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine

which request is serviced. The following table shows the internal polling sequence in the same priority level and

the interrupt vector address.

Chapter 6. Interrupt System

Interrupt Sources, vector address, priority and polling sequence Table

Interrupt

Source

Interrupt

Vector

address

Priority

within

level

Interrupt Priority

setting(IPH, IP)

Priority 0

(lowest)

Priority

Priority 3

(highest)

Interrupt Request

Interrupt Enable

Control Bit

External

interrupt 0

(INT0)

0003H 0(highest)

PX0H,PX0

0,0

0,1

1,0

1,1

IE0

EX0/EA

Timer 0

000BH

PT0H,PT0

0,0

0,1

1,0

1,1

TF0

ET0/EA

External

interrupt 1

(INT1)

0013H

PX1H,PX1

0,0

0,1

1,0

1,1

IE1

EX1/EA

Timer1

001BH

PT1H, PT1

0, 0

0, 1

1, 0

1, 1

TF1

ET1/EA

UART

0023H

PSH, PS

0, 0

0, 1

1, 0

1, 1

RI+TI

ES/EA

ADC/SPI 002BH

PADC_SPIH,

PADC_SPI

0, 0

0, 1

1, 0

1, 1

ADC_FLAG+SPIF

(EADCI+ESPI) /

EADC_SPI / EA

PCA/

LVD

0033H

6 (lowest)

PPCA_LVDH,

PPCA_LVD

0, 0

0, 1

1, 0

1, 1

CF+CCF0+CCF1+

CCF2+CCF3+LVDF

(ECF+ECCF0+E

CCF1+ECCF2+

ECCF3+ELVD)/

EPCA_LVD/EA

125

STC12LE5616AD Datasheet(PDF) 125 Page - STCmicro Technology Co,.Ltd

STC12LE5616AD Datasheet(HTML) 125 Page - STCmicro Technology Co,.Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL