S75WS256NDFBAWMB datasheet(113/216 Pages) SPANSION

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February 17, 2005 S75WS-N-00_00_A0

S75WS256Nxx Based MCPs

111

Data

Sheet

19.3.1

Read Mode Setting

On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting

allows the system to enable or disable burst mode during system operations. Configuration Bit

CR0.15 determines this setting: 1 for asynchronous mode, 0 for synchronous mode.

19.3.2

Programmable Wait State Configuration

The programmable wait state feature informs the device of the number of clock cycles that must

elapse after AVD# is driven active before data will be available. This value is determined by the

input frequency of the device. Configuration Bit CR1.0 & CR0.13–CR0.11 determine the set-

ting (see Table 19.7).

The wait state command sequence instructs the device to set a particular number of clock cycles

for the initial access in burst mode. The number of wait states that should be programmed into

the device is directly related to the clock frequency.

Notes:

1. Upon power-up or hardware reset, the default setting is twelve wait states.

2. All other but setting are reserved.

It is recommended that the wait state command sequence be written, even if the default wait

state value is desired, to ensure the device is set as expected. A hardware reset will set the wait

state to the default setting.

19.3.3

Programmable Wait State

The host system should set CR1.0 & CR0.13-CR0.11 to 1100/1010/1000 for a clock frequency

of 80/66/54 MHz for the system/device to execute at maximum speed.

19.3.4

Boundary Crossing Latency

Additional wait states must be inserted to account for boundary crossing latency. This is done by

setting CR0.14 to a ‘1’ (default). If required, CR0.14 can be changed to a ‘0’ to remove the

boundary crossing latency.

Table 19.7 Programmable Wait State Settings

CR1.0

CR0.13

CR0.12

CR0.11

Total Initial Access Cycles

Reserved

12 (default)

Reserved

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