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S75WS256NDFBAWMB Datasheet(PDF) 175 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 175 Page - SPANSION |
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175 / 216 page  February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 173 Advance Information Notes: 1. See How Extended Timings Impact CellularRAM™ Operation below. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. Table 34.4 Asynchronous Write Cycle Timing Requirements Parameter Symbol 70 ns/80 MHz 85 ns/66 MHz Units Notes Min Max Min Max Address and ADV# Low Setup Time tAS 00 ns Address Hold from ADV# Going High tAVH 55 ns Address Setup to ADV# Going High tAVS 10 10 ns Address Valid to End of Write tAW 70 85 ns LB#/UB# Select to End of Write tBW 70 85 ns Maximum CE# Pulse Width tCEM 44 µs 1 CE# Low to Wait Valid tCEW 1 7.5 1 7.5 ns Async Address-to-Burst Transition Time tCKA 70 85 ns CE# Low to ADV# High tCVS 10 10 ns Chip Enable to End of Write tCW 70 85 ns Data Hold from Write Time tDH 00 ns Data Write Setup Time tDW 23 23 ns 1 Chip Disable to Wait High-Z Output tHZ 88 ns Chip Enable to Low-Z Output tLZ 10 10 ns 3 End Write to Low-Z Output tOW 55 ns 3 ADV# Pulse Width tVP 10 10 ns ADV# Pulse Width High tVPH 10 10 ns ADV# Setup to End of Write tVS 70 85 ns Write Cycle Time tWC 70 85 ns Write to DQ High-Z Output tWHZ 88 ns 2 Write Pulse Width tWP 46 55 ns 1 Write Pulse Width High tWPH 10 10 ns Write Recovery Time tWR 00 ns |
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