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S75WS256NDFBAWMB Datasheet(PDF) 176 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 176 Page - SPANSION |
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176 / 216 page  174 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Ad van c e Inf o rmation 34.1 Timing Diagrams Table 34.5 Burst Write Cycle Timing Requirements Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units Notes Min Max Min Max CE# High between Subsequent Mixed-Mode Operations tCBPH 55 ns CE# Low to Wait Valid tCEW 1 7.5 1 7.5 ns Clock Period tCLK 12.5 15 ns CE# Setup to CLK Active Edge tCSP 45 ns Hold Time from Active CLK Edge tHD 22 ns Chip Disable to Wait High-Z Output tHZ 88 ns CLK Rise or Fall Time tKHKL 1.6 1.6 ns Clock to Wait Valid tKHTL 911 ns CLK High or Low Time tKP 33 ns Setup Time to Activate CLK Edge tSP 33 ns Figure 34.3 Initialization Period Table 34.1 Initialization Timing Parameters Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units Notes Min Max Min Max Initialization Period (required before normal operations) tPU 150 150 µs tPU VCC, VCCQ = 1.7V VCC (MIN) Device ready for normal operation |
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