S75WS256NDFBAWMB datasheet(174/216 Pages) SPANSION

174 / 216 page

172

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Notes:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH

or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the

High-Z (VCCQ/2) level toward either VOH or VOL.

Table 34.3 Burst Read Cycle Timing Requirements

Parameter

Symbol

70ns/80 MHz

85ns/66 MHz

Units

Notes

Min

Max

Min

Max

Burst to Read Access Time (Variable Latency)

tABA

CLK to Output Delay

tACLK

911

Address Setup to ADV# High

tAVS

Burst OE# Low to Output Delay

tBOE

CE# High between Subsequent Mixed-Mode Operations

tCBPH

CE# Low to Wait Valid

tCEW

7.5

CLK Period

tCLK

12.5

CE# Setup Time to Active CLK Edge

tCSP

Hold Time from Active CLK Edge

tHD

Chip Disable to DQ and Wait High-Z Output

tHZ

CLK Rise or Fall Time

tKHKL

1.6

CLK to Wait Valid

tKHTL

911

CLK to DQ High-Z Output

tKHZ

383

CLK to Low-Z Output

tKLZ

252

Output Hold from CLK

tKOH

CLK High or Low Time

tKP

Output Disable to DQ High-Z Output

tOHZ

Output Enable to Low-Z Output

tOLZ

Setup Time to Active CLK Edge

tSP

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