R7F100LLL3CFB datasheet(112/148 Pages) RENESAS

112 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 112 of 145

Oct 31, 2025

2.5.3

Serial interface IICA

1. I2C standard mode

Note 1.

The first clock pulse is generated after this period when the start or restart condition is detected.

Note 2.

The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an

acknowledgment (ACK) signal.

Remark 1.

The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.

Cb = 400 pF, Rb = 2.7 kΩ

Remark 2.

n = 0, 1

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

SCLA0 clock frequency

fSCL

Standard mode: fCLK ≥ 1 MHz

100

kHz

Setup time of restart condition

tSU:STA

4.7

µs

Hold timeNote 1

tHD:STA

4.0

µs

Hold time when SCLA0 is low

tLOW

4.7

µs

Hold time when SCLA0 is high

tHIGH

4.0

µs

Data setup time (reception)

tSU:DAT

250

Data hold time (transmission)Note 2

tHD:DAT

03.45

µs

Setup time of stop condition

tSU:STO

4.0

µs

Bus-free time

tBUF

4.7

µs

R7F100LLL3CFB Datasheet(PDF) 112 Page - Renesas Technology Corp

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