R7F100LLL3CFB datasheet(113/148 Pages) RENESAS

113 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 113 of 145

Oct 31, 2025

2. I2C fast mode

Note 1.

The first clock pulse is generated after this period when the start or restart condition is detected.

Note 2.

The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an

acknowledgment (ACK) signal.

Remark 1.

The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.

Cb = 320 pF, Rb = 1.1 kΩ

Remark 2.

n = 0, 1

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

SCLAn clock frequency

fSCL

Fast mode: fCLK ≥ 3.5 MHz

1.8 V ≤ VDD ≤ 5.5 V

400

kHz

Setup time of restart condition

tSU:STA

1.8 V ≤ VDD ≤ 5.5 V

0.6

µs

Hold timeNote 1

tHD:STA

1.8 V ≤ VDD ≤ 5.5 V

0.6

µs

Hold time when SCLAn is low

tLOW

1.8 V ≤ VDD ≤ 5.5 V

1.3

µs

Hold time when SCLAn is high

tHIGH

1.8 V ≤ VDD ≤ 5.5 V

0.6

µs

Data setup time (reception)

tSU:DAT

1.8 V ≤ VDD ≤ 5.5 V

100

Data hold time (transmission)Note 2

tHD:DAT

1.8 V ≤ VDD ≤ 5.5 V

0.9

µs

Setup time of stop condition

tSU:STO

1.8 V ≤ VDD ≤ 5.5 V

0.6

µs

Bus-free time

tBUF

1.8 V ≤ VDD ≤ 5.5 V

1.3

µs

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