R7F100LLL3CFB datasheet(114/148 Pages) RENESAS

114 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 114 of 145

Oct 31, 2025

3. I2C fast mode plus

Note 1.

The first clock pulse is generated after this period when the start or restart condition is detected.

Note 2.

The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an

acknowledgment (ACK) signal.

Remark 1.

The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.

Cb = 120 pF, Rb = 1.1 kΩ

Remark 2.

n = 0, 1

IICA serial transfer timing

Remark

n = 0, 1

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

SCLAn clock frequency

fSCL

Fast mode plus: fCLK ≥ 10 MHz

2.7 V ≤ VDD ≤ 5.5 V

1000

kHz

Setup time of restart condition

tSU:STA

2.7 V ≤ VDD ≤ 5.5 V

0.26

µs

Hold timeNote 1

tHD:STA

2.7 V ≤ VDD ≤ 5.5 V

0.26

µs

Hold time when SCLAn is low

tLOW

2.7 V ≤ VDD ≤ 5.5 V

0.5

µs

Hold time when SCLAn is high

tHIGH

2.7 V ≤ VDD ≤ 5.5 V

0.26

µs

Data setup time (reception)

tSU:DAT

2.7 V ≤ VDD ≤ 5.5 V

Data hold time (transmission)Note 2

tHD:DAT

2.7 V ≤ VDD ≤ 5.5 V

0.45

µs

Setup time of stop condition

tSU:STO

2.7 V ≤ VDD ≤ 5.5 V

0.26

µs

Bus-free time

tBUF

2.7 V ≤ VDD ≤ 5.5 V

0.5

µs

tSU:DAT

tHD:STA

Restart

condition

SCLAn

SDAAn

tLOW

tHIGH

tSU:STA

tHD:STA

tSU:STO

Stop

condition

Stop

condition

Start

condition

tHD:DAT

tBUF

R7F100LLL3CFB Datasheet(PDF) 114 Page - Renesas Technology Corp

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