R7F100LLL3CFB datasheet(116/148 Pages) RENESAS

116 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 116 of 145

Oct 31, 2025

Note 1.

This value does not include the quantization error (±1/2 LSB).

Note 2.

When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D

converted, the maximum values are as follows.

Overall error: Add ±3 LSB to the maximum value.

Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value.

Note 3.

When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows.

Overall error: Add ±10 LSB to the maximum value.

Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value.

Integral linearity error: Add ±4 LSB to the maximum value.

Note 4.

When AVREFP < VDD, the maximum values are as follows.

Note 5.

When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the

sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time.

Note 6.

This value is indicated as a ratio (%FSR) to the full-scale value.

(TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V,

reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1),

target pins: internal reference voltage and temperature sensor output voltage)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

Resolution

RES

bit

Conversion clock

fAD

132

MHz

Overall errorNotes 1, 2, 3, 4

AINL

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

±7.5

LSB

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±9.0

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±9.0

LSB

Conversion timeNote 5

tCONV

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

2.0

µs

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

2.0

µs

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

2.0

µs

Zero-scale errorNotes 1, 2, 3, 4, 6

EZS

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

±0.17

%FSR

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

Full-scale errorNotes 1, 2, 3, 4, 6

EFS

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

±0.17

%FSR

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

Integral linearity errorNotes 1, 3, 4 ILE

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

±3.0

LSB

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±3.0

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±3.0

LSB

Differential linearity errorNote 1

DLE

12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V

±1.0

LSB

2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±1.0

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±1.0

LSB

Analog input voltage

VAIN

0AVREFP

Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum

value.

Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

R7F100LLL3CFB Datasheet(PDF) 116 Page - Renesas Technology Corp

R7F100LLL3CFB Datasheet(HTML) 116 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL