R7F100LLL3CFB datasheet(117/148 Pages) RENESAS

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RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 117 of 145

Oct 31, 2025

2. Low-voltage modes 1 and 2

Note 1.

If the internal reference voltage, temperature sensor output voltage, or TSCAP voltage of the CTSU is to be A/D converted,

VDD must be at least 1.8 V.

Note 2.

This value does not include the quantization error (±1/2 LSB).

Note 3.

When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D

converted, the maximum values are as follows. If the CTSU TSCAP voltage is to be A/D converted, VDD must be at least

1.8 V.

Overall error: Add ±3 LSB to the maximum value.

Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value.

Note 4.

When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows.

Overall error: Add ±10 LSB to the maximum value.

Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value.

Integral linearity error: Add ±4 LSB to the maximum value.

Note 5.

When AVREFP < VDD, the maximum values are as follows.

(TA = -40 to +105°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V,

reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1),

target pins: internal reference voltageNote 1and temperature sensor output voltageNote 1)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

Resolution

RES

bit

Conversion clock

fAD

124

MHz

Overall errorNotes 2, 3, 4, 5

AINL

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±9

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±9

LSB

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

±11.5

LSB

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

±12.0

LSB

Conversion timeNote 6

tCONV

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

3.33

µs

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

5.0

µs

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

10.0

µs

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

20.0

µs

Zero-scale errorNotes 2, 3, 4, 5, 7

EZS

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

±0.27

%FSR

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

±0.28

%FSR

Full-scale errorNotes 2, 3, 4, 5, 7

EFS

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±0.21

%FSR

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

±0.27

%FSR

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

±0.28

%FSR

Integral linearity errorNotes 2, 4, 5 ILE

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±4.0

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±4.0

LSB

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

±4.5

LSB

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

±4.5

LSB

Differential linearity errorNote 2

DLE

12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V

±1.5

LSB

2.4 V ≤ AVREFP = VDD ≤ 5.5 V

±1.5

LSB

1.8 V ≤ AVREFP = VDD ≤ 5.5 V

±2.0

LSB

1.6 V ≤ AVREFP = VDD ≤ 5.5 V

±2.0

LSB

Analog input voltage

VAIN

0AVREFP

Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum

value.

Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

R7F100LLL3CFB Datasheet(PDF) 117 Page - Renesas Technology Corp

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