MC68HC705P9CS datasheet(115/160 Pages) FREESCALE

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Timer

I/O Registers

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Timer

115

9.7.6 Output Compare Registers

When the value of the 16-bit counter matches the value in the read/write

output compare registers (OCRH and OCRL), the planned TCMP pin

action takes place. Writing to OCRH before writing to OCRL inhibits

timer compares until OCRL is written. Reading or writing to OCRL after

reading the timer status register clears the output compare flag (OCF).

To prevent OCF from being set between the time it is read and the time

the output compare registers are updated, use the following procedure:

1. Disable interrupts by setting the I bit in the condition code register.

2. Write to OCRH. Compares are now inhibited until OCRL is written.

3. Clear bit OCF by reading the timer status register (TSR).

4. Enable the output compare function by writing to OCRL.

5. Enable interrupts by clearing the I bit in the condition code register.

$0016

Bit 7

54321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Unaffected by reset

$0017

Bit 7

54321

Bit 0

Read:

Bit 7

54321

Bit 0

Write:

Reset:

Unaffected by reset

Figure 9-17. Output Compare Registers (OCRH and OCRL)

Freescale Semiconductor, Inc.

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