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C6416 Datasheet(PDF) 101 Page - Texas Instruments |
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C6416 Datasheet(HTML) 101 Page - Texas Instruments |
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101 / 134 page  SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 101 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUTx CEx ABE[7:0] or BBE[1:0] AEA[22:3] or BEA[20:1] AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ MRS value 11 8 12 5 1 MRS 11 8 12 4 1 † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 33. SDRAM MRS Command for EMIFA and EMIFB† |
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