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C6416 Datasheet(PDF) 102 Page - Texas Instruments |
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C6416 Datasheet(HTML) 102 Page - Texas Instruments |
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102 / 134 page ![]() SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) End Self-Refresh Self Refresh 13 13 AECLKOUTx ACEx ABE[7:0] AEA[22:14, 12:3] AEA13 AED[63:0] AAOE/ASDRAS/ASOE‡ AARE/ASDCAS/ASADS/ ASRE‡ AAWE/ASDWE/ASWE‡ ASDCKE ≥ TRAS cycles † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 34. SDRAM Self-Refresh Timing for EMIFA Only† |
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