C6416 datasheet(103/134 Pages) TI1

103 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

103

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

HOLD/HOLDA TIMING

timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules† (see Figure 35)

NO.

MIN

MAX

UNIT

toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low

*This parameter is not production tested.

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles

for EMIFA and EMIFB modules†‡§ (see Figure 35)

NO.

PARAMETER

MIN

MAX

UNIT

td(HOLDL-EMHZ)

Delay time, HOLD low to EMIF Bus high impedance

2E*

¶*

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to HOLDA low

2E*

td(HOLDH-EMLZ)

Delay time, HOLD high to EMIF Bus low impedance

2E*

7E*

td(EMLZ-HOLDAH)

Delay time, EMIF Bus low impedance to HOLDA high

2E*

td(HOLDL-EKOHZ)

Delay time, HOLD low to ECLKOUTx high impedance

2E*

¶*

td(HOLDH-EKOLZ)

Delay time, HOLD high to ECLKOUTx low impedance

2E*

7E*

*This parameter is not production tested.

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.

‡ For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.

For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and

BAWE/BSDWE/BSWE, BSOE3, and BPDT.

§ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.

¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay

time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

C64x

ECLKOUTx‡

(EKxHZ = 0)

ECLKOUTx‡

(EKxHZ = 1)

† For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and

BAWE/BSDWE/BSWE, BSOE3, and BPDT.

‡ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.

Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB

C6416 Datasheet(PDF) 103 Page - Texas Instruments

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