C6416 datasheet(106/134 Pages) TI1

106 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

106

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

RESET TIMING (CONTINUED)

ECLKOUT2

CLKOUT4

CLKOUT6

RESET

ECLKIN

Low Group‡

Z Group‡§

Boot and Device

Configuration Inputs§¶

EMIF Z Group‡§

EMIF High Group‡

EMIF Low Group‡

ECLKOUT1

† These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., ECLKIN, ECLKOUT1,

and ECLKOUT2].

‡ EMIF Z group consists of:

AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,

AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.

EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)

EMIF low group consists of:

ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)

Low group consists of:

XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)

is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO

pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section

of this data sheet.

Z group consists of:

HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,

DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,

TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,

GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,

HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,

and URCLAV.

§ If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15,

16, and 17.

¶ Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5.

The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.

The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.

Figure 37. Reset Timing†

C6416 Datasheet(PDF) 106 Page - Texas Instruments

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