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CP3SP33SMS/NOPB Datasheet(PDF) 207 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 207 Page - Texas Instruments

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CP3SP33
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SNOSCW5 – MAY 2013
IRQ/IST
The IRQ bit and IST field indicate the interrupt source of the highest priority interrupt
currently pending and enabled in the CICENn register. Table 22-18 shows the several
interrupt codes when the encoding for all interrupt sources is enabled (CICEN = FFFFh).
Table 22-18. Highest Priority Interrupt Code
IRQ
IST3:0
CAN Interrupt Request
0
0000
No interrupt request
1
0000
Error interrupt
1
0001
Buffer 0
1
0010
Buffer 1
1
0011
Buffer 2
1
0100
Buffer 3
1
0101
Buffer 4
1
0110
Buffer 5
1
0111
Buffer 6
1
1000
Buffer 7
1
1001
Buffer 8
1
1010
Buffer 9
1
1011
Buffer 10
1
1100
Buffer 11
1
1101
Buffer 12
1
1110
Buffer 13
1
1111
Buffer 14
22.10.15 CAN Error Counter Register n (CANECn)
The CANECn register reports the values of the CAN Receive Error Counter and the CAN Transmit Error
Counter.
15
8M M7
0
REC
TEC
0
R
REC
The CAN Receive Error Counter field reports the value of the receive error counter.
TEC
The CAN Transmit Error Counter field reports the value of the transmit error counter.
22.10.16 CAN Error Diagnostic Register n (CEDIAGn)
The CEDIAGn register reports information about the last detected error. The CAN module identifies the
field within the CAN frame format in which the error occurred, and it identifies the bit number of the
erroneous bit within the frame field. The APB bus master has read-only access to this register, and all bits
are cleared on reset.
15
14
13
12
11
10
9
4 3
0
Reserved
DRIVE
MON
CRC
STUFF
TXE
EBID
EFID
0
R
Copyright © 2013, Texas Instruments Incorporated
Dual CAN Interfaces
207
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