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CP3SP33SMS/NOPB Datasheet(PDF) 209 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 209 Page - Texas Instruments

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CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
STUFF
The Stuff Error bit indicates whether the bit stuffing rule was violated at the time the error
occurred. Note that certain bit fields do not use bit stuffing and therefore this bit may be ignored
for those fields.
0 – No bit stuffing error.
1 – The bit stuffing rule was violated at the time the error occurred.
CRC
The CRC Error bit indicates whether the CRC is invalid. This bit should only be checked if the
EFID field shows the code of the ACK field.
0 – No CRC error occurred.
1 – CRC error occurred.
MON
The Monitor bit shows the bus value on the CANnRX pin as sampled by the CAN module at the
time of the error.
DRIVE
The Drive bit shows the output value on the CANnTX pin at the time of the error. Note that a
receiver will not drive the bus except during ACK and during an active error flag.
22.10.17 CAN Timer Register n (CTMRn)
The CTMR register reports the current value of the Time Stamp Counter as described in Section 22.8.
15
0
CTMR15:0
0
R
The CTMRn register is a free running 16-bit counter. It contains the number of CAN bits recognized by the
CAN module since the register has been cleared. The counter starts to increment from the value 0000h
after a hardware reset. If the Timer Stamp Enable bit (TSTPEN) in the CAN global configuration register
(CGCRn) is set, the counter will also be cleared on a message transfer of the message buffer 0
The contents of CTMRn are captured into the Time Stamp register of the message buffer after
successfully sending or receiving a frame, as described in Section 22.8.
22.11 System Start-Up and Multi-Input Wake-Up
After system start-up, all CAN-related registers are in their reset state. The CAN module can be enabled
after all configuration registers are set to their desired value. The following initial settings must be made:
•
Configure the CAN Timing register (CTIMn). See Section 22.2.6.
•
Configure every buffer to its function as receive/transmit. See Section 22.10.1.
•
Set the acceptance filtering masks. See Section 22.4.
•
Enable the CAN interface. See Section 22.10.6.
Before disabling the CAN module, software must make sure that no transmission is still pending.
NOTE
Activity on the CAN bus can wake up the device from a low-power mode by selecting the
CANnRX pin as an input to the Multi-Input Wake-Up module. In this case, the CAN module
must not be disabled before entering the low-power mode. Disabling the CAN module also
disables the CANnRX pin. As an alternative, the CANnRX pin can be connected to any other
input pin of the Multi-Input Wake-Up module. This input channel must then be configured to
trigger a wake-up event on a falling edge (if a dominant bit is represented by a low level). In
this case, the CAN module can be disabled before entering the low-power mode. After
waking up, software must enable the CAN module again. All configuration and buffer
registers still contain the same data they held before the low-power mode was entered.
Copyright © 2013, Texas Instruments Incorporated
Dual CAN Interfaces
209
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