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CP3SP33SMS/NOPB Datasheet(PDF) 205 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 205 Page - Texas Instruments |
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205 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 When an extended frame is received from the CAN bus, all BMSKn bits BM28:0, IDE, RTR, and XRTR are used to mask the incoming message. In this case, the RTR bit in the BMSKn register corresponds to the SRR bit in the message. The XRTR bit in the BMSKn register corresponds to the RTR bit in the message. During the reception of standard frames, only the BMSKn bits BM28:18, RTR, and IDE are used. In this case, the BM28:18 bits in the BMSKn register correspond to the ID10:0 bits in the message. Basic Mask BM28:18 RTR IDE BM17:0 XRTR Standard Frame ID10:0 RTR IDE Unused Extended Frame ID28:18 SRR IDE ID17:0 RTR 22.10.10 CAN Interrupt Enable Register n (CIENn) The CIENn register enables the transmit/receive interrupts of the message buffers 0 through 14 as well as the CAN Error Interrupt. 15 14 0 EIEN IEN 0 R/W EIEN The Error Interrupt Enable bit allows the CAN module to interrupt the CPU if any kind of CAN receive/transmit errors are detected. This causes any error status change in the error counter registers REC/TEC is able to generate an error interrupt. 0 – The error interrupt is disabled and no error interrupt will be generated. 1 – The error interrupt is enabled and a change in REC/TEC will cause an interrupt to be generated. IEN The Buffer Interrupt Enable bits allow software to enable/disable the interrupt source for the corresponding message buffer. For example, IEN14 controls interrupts from buffer14, and IEN0 controls interrupts from buffer0. 0 – Buffer as interrupt source disabled. 1 – Buffer as interrupt source enabled. 22.10.11 CAN Interrupt Pending Register n (CIPNDn) The CIPNDn register indicates any CAN Receive/Transmit Interrupt Requests caused by the message buffers 0..14 and CAN error occurrences. 15 14 0 EIPND IPND 0 R EIPND The Error Interrupt Pending field indicates the status change of TEC/REC and will execute an error interrupt if the EIEN bit is set. Software has the responsibility to clear the EIPND bit using the CICLRn register. 0 – CAN status is not changed. 1 – CAN status is changed. IPND The Buffer Interrupt Pending bits are set by the CAN module following a successful transmission or reception of a message to or from the corresponding message buffer. For example, IPND14 corresponds to buffer14, and IPND0 corresponds to buffer0. 0 – No interrupt pending for the corresponding message buffer. 1 – Message buffer has generated an interrupt. Copyright © 2013, Texas Instruments Incorporated Dual CAN Interfaces 205 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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