CP3SP33SMSSLASHNOPB datasheet(216/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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23.1.3 ADC Clock Generation

The DELAY2 block generates ADC Clock, which is the clock used internally by the ADC module. ADC

Clock is derived from either:

•

PCLK Clock—a programmable divider is available to generate the 12 MHz clock required by the ADC

from the PCLK Clock.

•

Auxiliary Clock 1—may be used to perform conversions when the PCLK Clock is slowed down or

suspended in low-power modes.

The DELAY2 block receives the clock source selected by the CLKSEL bit of the ADCACR register and

adds a number of asynchronous incremental delay units specified in the ADC_DELAY2 field of the

ADCSCDLY register. This delayed clock (ADC Clock) then drives the TRIGGER, ADC, and ADC

SEQUENCER blocks. ADC Clock also drives the ADC_DIV clock divider, which generates the clock which

drives the DELAY1 block.

Because the ADCRESLT FIFO is driven by PCLK Clock (not ADC Clock), a conversion result will not

propagate to the output of the FIFO when PCLK Clock is suspended.

23.1.4 ADC Voltage References

The ADC block has positive and negative voltage reference inputs, VREFP and VREFN. In single-ended

mode, only VREFP is used. An analog multiplexer allows selecting an external VREF pin, the analog

supply voltage ADVCC, or the analog inputs ADC0 or ADC1 as the positive voltage reference, as

controlled by the PREF_CFG field of the ADCGCR register. Another analog multiplexer allows selecting

the analog ground ADGND or the analog inputs ADC2 or ADC3 as the negative voltage reference, as

controlled by the NREF_CFG field of the ADCGCR register.

23.2 Operation in Low-Power Modes

To reduce the level of switching noise in the environment of the ADC, it is possible to operate the

CP3SP33 in low-power modes, in which the PCLK Clock is slowed or switched off. Under these

conditions, Auxiliary Clock 1 can be selected as the clock source for the ADC module, however

conversion results cannot be read by the system while the PCLK Clock is suspended. To operate in a low-

power mode:

1. ADC is configured and a conversion is primed or triggered.

2. A low-power mode is entered.

3. ADC conversion completes and a wake-up signal is asserted to the MIWU unit.

4. Device wakes up and processes the conversion result.

To conserve power, the ADC should be disabled before entering a low-power mode if its function is not

required.

23.3 Freeze Mode

When Freeze mode is entered, the ADC will exhibit the following specific behavior:

•

The automatic clear-on-read function of the result register (ADCRESLT) is disabled.

•

The FIFO is updated as usual, and an interrupt for a completed conversion can be asserted.

216

Analog-to-Digital Converter

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