CP3SP33SMSSLASHNOPB datasheet(217/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

23.4 ADC Register Set

Table 23-1 lists the ADC registers.

Table 23-1. ADC Registers

Name

Address

Description

ADCGCR

FF AC00h

ADC Global Configuration Register

ADCACR

FF AC04h

ADC Auxiliary Configuration Register

ADCCNTRL

FF AC08h

ADC Conversion Control Register

ADCSTART

FF AC0Ch

ADC Start Conversion Register

ADCSCDLY

FF AC10h

ADC Start Conversion Delay Register

ADCRESLT

FF AC14h

ADC Result Register

23.4.1 ADC Global Configuration Register (ADCGCR)

The ADCGCR register is a 16-bit, read/write register that controls the basic operation of the interface. The

APB bus master has read/write access to the ADCGCR register. After reset this register is cleared.

12 11

10 9

7 6

MUXOUTEN

INTEN

NREF_CFG

PREF_CFG

Reserved

MUX_CFG

DIFF

ADCIN

CLKEN

The Clock Enable bit controls whether the ADC module is running. When this bit is clear, all

ADC clocks are disabled, the ADC analog circuits are in a low-power state, and ADC

registers (other than the ADCGCR and AGCACR registers) are not writeable. Clearing this

bit reinitializes the ADC state machine and cancels any pending trigger event. Setting this

bit enables the ADC clocks and powers up the ADC analog circuits. The converter is

operational within 0.25 µs of being enabled.

0 – ADC disabled.

1 – ADC enabled.

ADCIN

The ADCIN bit selects the source of the ADC input. When the bit is clear, the source is the

10-channel Input Multiplexer. When the bit is set, the source is the ADCIN pin.

0 – ADC input is from 10-channel multiplexer.

1 – ADC input is from ADCIN pin.

DIFF

The Differential Operation Mode bit and the MUX_CFG field configure the analog circuits of

the ADC module. When this bit is clear, the ADC module operates in single-ended mode.

When this bit is set, the ADC operates in differential mode.

0 – Single-ended mode.

1 – Differential mode.

MUX_CFG The Multiplexer Configuration field and the DIFF bit configure the analog circuits of the ADC

module, as shown below.

Channel

(DIFF = 1)

MUX_CFG

(DIFF = 0)

0000

0001

0010

0011

0100

0101

0110

0111

Analog-to-Digital Converter

217

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