CP3SP33SMSSLASHNOPB datasheet(220/407 Pages) TI1

220 / 407 page

4 511 170 us

12 MHz

u u

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

23.4.5 ADC Start Conversion Delay Register (ADCSCDLY)

The ADCSCDLY register is a 16-bit, read/write register that controls critical timing parameters for the

operation of the ADC module. After reset, the register is cleared.

14 13

5 4

ADC_DIV

ADC_DELAY1

ADC_DELAY2

The ADC Delay 2 field specifies the delay between the ADC module clock source

(either PCLK Clock after a programmable divider or Auxiliary Clock 1) and the ADC

clock. The range of effective values for this field is 0 to 20. Values above 20 produce

the same delay as 20, which is about 42 ns.

ADC_DELAY1

The ADC Delay 1 field specifies the number of clock periods by which the trigger event

will be delayed before initiating a conversion. The timebase for this delay is the ADC

clock (12 MHz) divided by the ADC_DIV divisor. The ADC_DELAY1 field has 9 bits,

which corresponds to a maximum delay of 511 clock periods.

ADC_DIV

The ADC Clock Divisor field specifies the divisor applied to the ADC clock (12 MHz) to

generate the clock used to drive the DELAY1 block. The field is biased by 1, so the

divisor selected by the ADC_DIV field may be 1, 2, 3, or 4. With a module clock of 12

MHz, the maximum delay which can be provided by ADC_DIV and ADC_DELAY

settings is:

23.4.6 ADC Result Register (ADCRESLT)

The ADCRESLT register is a 16-bit, read-only register that includes the software-visible end of a 4-word

FIFO. Conversion results are loaded into the FIFO from the ADC and unloaded when software reads the

ADCRESLT register. The ADCRESLT register is read-only. The defined fields in this register are cleared

when the register is read. After reset, this register is clear.

ADC_DONE

ADC_OFLW

Reserved

SIGN

ADC_RESULT

The ADC Result field holds a 12-bit value for the conversion result. If the ADC_DONE

bit is clear, there is no valid result in this field, and the field will have a value of 0. The

ADC_RESULT field and the SIGN bit together form the software-visible end of the

ADC FIFO.

SIGN

The Sign bit indicates whether the (minus) – input has a voltage greater than the (plus)

+ input (differential mode only). For example if ADCGCR.MUX_CFG is 000b, ADC0 is

the + input and ADC1 is the – input. If the voltage on ADC0 is greater than the voltage

on ADC1, the SIGN bit will be 0; if the voltage on ADC0 is less than the voltage on

ADC1, the SIGN bit will be 1. In single-ended mode, this bit always reads as 0.

0 – In differential mode, + input has a voltage greater than the – input. In single-ended

mode, this bit is always 0.

1 – In differential mode, – input has a voltage greater than the + input.

ADC_OFLW

The ADC FIFO Overflow bit indicates whether the 4-word FIFO behind the ADCRESLT

This bit is cleared when the ADCRESLT register is read.

0 – FIFO overflow has not occurred.

1 – FIFO overflow has occurred.

220

Analog-to-Digital Converter

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 220 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 220 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL